Welcome to Shilpa's Homepage
About me
PhD student at The University of Texas at Dallas. I'm in the Computer Engineering department and my advisor is Dr. Dinesh Bhatia. I received a Master's Degree in Computer Engineering from The University of Texas at Dallas in 2005.
Courses I've taken
Microprocessor Systems
Project: Implementation of IP forwarding engine using Altera NIOS processor
VHDL Modeling
Project: Implementation of UART Transmitter & Receiver
Digital Signal Processing I
Project: FIR Filter Design using MATLAB
VLSI Design
Project: VLSI implementation of a CORDIC converter
Computer Architecture
Project: Implementation and analysis of L3 Cache using the SimpleScalar tool
Advanced Operating Systems
Projects: Implementation of the Lamport's Mutual Exclusion Algorithm on a
distributed system
Implementation of the Koo-Toueg Checkpointing Algorithm and
the Chandy Lamport termination detection algorithm on a
distributed system
Physical Design Automation of VLSI Systems
Project: Implementation (in C) of the Simulated Annealing Algorithm for circuit bipartitioning
Performance of Computer Networks & Systems
Project: Implementation of Event Driven Markovian Queueing systems.
Design of Computer Algorithms
My research
Thermal Aware FPGA Architecture and CAD
The focus of our research is on the management of temperature distribution across FPGAs. We are developing a comprehensive framework involving innovative algorithms and architectures to create a robust system level approach to manage on-chip temperatures. Elevated thermal conditions are primarily due to increased power dissipation, uneven distribution of power sources and material properties. At the system level we tackle the problem by targeting the first two factors. Temperature management solutions require a light weight but accurate model of a device’s thermal activity. The model should be portable and computationally convenient. In that regard we have developed the ‘Node-Arc’ model targeted specifically for the reconfigurable FPGA fabric. It exploits uniformity in the logic element distribution in an FPGA to compute temperatures at various points in the fabric.
The response to temperature rise in a device can be static or dynamic in nature. Static techniques use a predetermined response based on estimated activity while dynamic methods intelligently modify their response based on current thermal conditions. Our methodology provides solutions on both fronts. In the static realm, we have developed a thermal aware placement tool that optimally distributes logic with an objective of reducing maximum on chip temperature and creating a more even thermal distribution. Our tool achieves upto 3.97 Degree Celsius reduction in maximum temperature. As power dissipation is paramount to thermal management we are also working on designing algorithms to accurately estimate FPGA power dissipation. Interconnect accounts for nearly 70% of the total power generated by an FPGA. Our models seek to estimate interconnect generated dynamic and static power. These estimates are prior to routing and are thus useful in placement tools and in the exploration of new routing architectures. The estimation framework is flexible to accommodate both static and dynamic power for a variety of routing structures. With regard to dynamic thermal management we are building intelligent systems that adapt to varying thermal conditions and actively minimize FPGA temperatures. Our solution tackles the problem at a range of granularities for an effective response with minimal performance and hardware overhead. We also exploit the flexibility of the reconfigurable fabric to tailor response mechanisms for varying activity profiles associated with different applications. Our goal is to develop a system that can observe trends in rising temperature and take proactive measures to prevent thermal failure.
Network on Chip
Implemented a multi core JPEG
compression system interconnected by a packet switched network on chip.
Developed generic interfaces to coordinate control and data information flow
between the cores and the network. The cores that were incorporated included a
JPEG engine, a processing core, a UART controller and a global memory. This work
is reported in a paper titled "Generic
Network Interface for Plug and Play NoC based Architecture" presented in the International Workshop on Applied Reconfigurable Computing 2006.
For more info check out: www.eac.utdallas.edu
(Source: http://www.embedded.com/showArticle.jhtml?articleID=159901371)
Courses I'm TAing
Spring 2008
EE 3320 - Digital Circuits
EE 2110 - Introduction to Digital Systems Lab
Office: ECSN 4.612 T 12:00 - 2:00pm
email me at
You can find me at
The University of Texas at Dallas
Department of Computer Engineering
Embedded and Adaptive Computing Lab
ECSN 4.612
2601 N. Floyd Rd, Richardson
TX - 75080