True Random numbers are required for a variety of security functions on future integrated circuits, ranging from RFID tags, to medical systems, to multi-core systems on chip. While many random number generators appear in the literature, there has not been a systematic analysis of the tradeoffs and vulnerabilities of the various circuit techniques in 45nm CMOS and below. If the random numbers in a cryptosystem can be guessed or forced, the security of the overall system can be seriously compromised. Trends in deep sub-micron CMOS toward increased process variability and noise have been proposed as sources of randomness, however a rigorous threat analysis needs to be performed based on the statistical properties of the variations and their potential correlation to channels accessible to the attacker. Side-channel analysis using power, timing, electromagnetics and other circuit-level emanations has been recently shown to be both a practical as well as theoretical threat. A related problem to TRNG is the unique identification of circuits based on their manufacturing variations. Physically Unclonable Functions (PUFs) have been developed which can generate a unique ID for each chip based on manufacturing variations. However, the design of PUFs in deep sub-micron CMOS with higher process variations, noise, and a wide range of operating voltages and temperatures has not been explored sufficiently to characterize potential new vulnerabilities. Other problems plaguing both TRNG and Chip ID are the impacts of data-remanence and aging which can be accelerated as an attack method. This talk presents analysis and circuit level solutions to many of these problems as well as posing some open problems for the future. This work is supported by SRC Task ID 1836.074, NSF 0964641 and the DHHS SHARPS program.
Wayne Burleson has been a Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst since 1990. He is also currently a Senior Fellow at AMD Research in Boston. He has degrees from MIT and the University of Colorado. He has worked as a custom chip designer and consultant in the semiconductor industry with VLSI Technology, DEC, Compaq/HP, Intel, Rambus and AMD, as well as several start-ups. Wayne was a visiting professor at ENST Paris in 1996/97, at LIRM Montpellier in 2003 and at EPFL Switzerland in 2010/12. His research is in the general area of VLSI, including circuits and CAD for low-power, interconnects, clocking, reliability, thermal effects, process variation and noise mitigation. He also conducts research in hardware security, reconfigurable computing, content-adaptive signal processing, RFID and multimedia instructional technologies. He teaches courses in VLSI Design, Embedded Systems and Security Engineering. Wayne has published over 180 refereed publications in these areas and is a Fellow of the IEEE for contributions in integrated circuit design and signal processing.