PRESENTATIONS

Tutorials (*5 invited):
1. Electrical and Reliability Characterization of Advanced MOS Devices
E. M. Vogel
Organized by Semyzen, Singapore, July 23-24, 2007.  *invited

2. Electrical Characterization of MOS Devices with Advanced Gate Stacks
E. M. Vogel
MIGAS International School on Advanced Microelectronics, Physical and Electrical Characterization of Materials and Devices for Silicon Nanoelectronics, (http://www.migas.inpg.fr/), Grenoble, France, June 11-17, 2005.  *invited

3. Characterization, Physical Modeling, and Assessment of Gate Oxide Reliability
E. M. Vogel
IEEE International Reliability Physics Symposium, Dallas, TX, April 7, 2002.  *invited

4. Ultra-thin Gate Oxide Reliability: Past and Present Trends in Characterization, Physical Modeling, and Assessment
E. M. Vogel
IEEE Integrated Reliability Workshop, Lake Tahoe, CA, Oct. 15, 2001.  *invited

5. Thin Gate Oxide Reliability
J. S. Suehle and E. M. Vogel
International Reliability Physics Symposium, Apr. 10, 2000.  *invited

Conferences (*23 invited)
2. In-situ XPS investigation of the “clean-up” effect through half-cycle ALD reactions
on III-V substrates
M. Milojevic, B. Brennan, F. S. Aguirre-Tostado, C. Hinkle, H. C. Kim, B. Lee, G. Hughes, E. M. Vogel, J. Kim, and R. M. Wallace
IEEE Semiconductor Interface Specialists Conference, 2008.

2. Performance Enhancement of n-Channel Invertion Type InxGa1-xAs MOSFET by Effective
Surface Passivation Using Ex-Situ Deposited Thin Amorphous Si Layer
A. M. Sonnet, C. L. Hinkle, M. N. Jivani, J. Kim, R. A. Chapman, R. M. Wallace and E. M. Vogel
IEEE Semiconductor Interface Specialists Conference, 2008.

3. Surface states, interface traps, and Fermi level pinning correlation to the interface oxidation states of Ga
C. L. Hinkle, A. M. Sonnet, E. M. Vogel, M. Milojevic, F. S. Aguirre-Tostado, J. Kim, R. M. Wallace, B. Brennan, and G. J. Hughes
IEEE Semiconductor Interface Specialists Conference, 2008.

4. Electrical and Physical Properties of High-k Gate Dielectrics on III-V Semiconductors
E. M. Vogel, C. L. Hinkle, A. Sonnet, F. S. Aguirre-Tostado, M. Milojevic, K. J. Choi, H. C. Kim, J. G. Wang, H. C. Floresca, J. Kim, M. J. Kim, and R.M. Wallace
American Vacuum Society Meeting, 2008. *invited

5. Electrical and Physical Properties of GaAs MOS Devices with Al2O3/a-Si Gate Dielectric Stacks
Eric M. Vogel, A. Sonnet, C. L. Hinkle, F. S. Aguirre-Tostado, M. Milojevic, J. Kim, and R.M. Wallace.
5th International Symposium on Advanced Gate Stack Technology, 2008.  *invited

6. Comparison of n-type and p-type GaAs oxide growth and its effects on frequency dispersion characteristics
C. L. Hinkle, A. M. Sonnet, M. Milojevic, F. S. Aguirre-Tostado, H. C. Kim, J. Kim, R. M. Wallace, and E. M. Vogel
Workshop on Dielectrics in Microelectronics, 2008.

7. Study of surface preparation for high-k dielectrics on GaAs
F. S. Aguirre-Tostado, M. Milojevic, S. McDonnell, R. Contreras-Guerrero, C. L.Hinkle, K. J. Choi, J. Kim, E. M. Vogel, A. Herrera-Gomez, R. M. Wallace, T. Yang, Y. Xuan and P.D. Ye
IEEE Semiconductor Interface Specialists Conference, 2007.

8. GaAs MOS Frequency Dispersion Reduction by Surface Oxide Removal and Passivation
C. L. Hinkle, A. M. Sonnet, E. M. Vogel, S. McDonnell, M. Milojevic, B. Lee, F. S. Aguirre-Tostado, K. J. Choi, J. Kim and R. M. Wallace
IEEE Semiconductor Interface Specialists Conference, 2007.

9. Characterization of Electrically Active Interfacial Defects in High-κ Gate Dielectrics
E. M. Vogel, A. M. Sonnet, and C. L. Hinkle
Electrochemical Society Meeting, 2007. *invited

10. GaAs Surface Modification by Arsenic Oxide Removal and Bond Conversion
C. L. Hinkle, M.  Milojevic, S. McDonnell, F. S. Aguirre-Tostado, A. M. Sonnet, R. M. Wallace, and E. M. Vogel
4th International Symposium on Advanced Gate Stack Technology, Dallas, TX, Sept. 27, 2007.

11. Metrology for Emerging Devices and Materials
E. M. Vogel
American Materials Failure Analysis (AMFA) Workshop, Phoenix, AZ, April 20, 2007. *invited

12. Metrology for Beyond CMOS: Emerging Devices and Materials
E. M. Vogel
53rd American Vacuum Society International Symposium, Nano-Manufacturing Topical Conference, San Francisco, CA, Nov. 12-16, 2006. *invited

13. Technology and Metrology for Beyond CMOS
E. M. Vogel
SEMATECH-SRC Topical Research Conference on Reliability, Austin, TX, Oct. 23, 2006. *invited

14. Precise Manipulation and Alignment of Single Nanowires for Device Fabrication
Q. Li, S.-M. Koo, C. A. Richter, M. D. Edelstein, J. J. Kopanski, J. S. Suehle, and E. M. Vogel
2006 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 11-12, 2006.

15. Schottky-contact silicon nanowire field effect transistor test structures
S.-M. Koo, C. A. Richter, Q. Li, M. D. Edelstein, and  E. M. Vogel
2006 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 11-12, 2006.

16. Work function characterization of TaSiN and TaCN electrodes using CV, IV, IPE and SKPM
H. D. Xiong, N. V. Nguyen, J. J. Kopanski, J. S. Suehle, and E. M. Vogel
Electrochemical Society Meeting, 2006.

17. Detection of Electron Trap Generation Due to Constant Voltage Stress on High-κ Gate Stacks
C. D. Young, S. Nadkarni, D. Heh, H. R. Harris, R. Choi, J. J. Peterson, J. H. Sim, S. A. Krishnan, J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G. A. Brown, and G. Bersuker
IEEE International Reliability Physics Symposium, 2006.

18. Metrology for new microelectronic materials
E. M. Vogel
American Physical Society Spring Meeting, Baltimore, MD, March 14, 2006. *invited

19. Electrical Characterization of Defects in High-k Gate Dielectrics
E. M. Vogel
International Semiconductor Device Research Symposium, Bethesda, MD, Dec. 7, 2005. *invited

20. Detection of trap generation in high-kappa gate stacks
C. D. Young, S. Nadkarni, D. Heh, H. R. Harris, R. Choi, J. J. Peterson, J. H. Sim, S. A. Krishnan, J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G. A. Brown, and G. Bersuker
IEEE Integrated Reliability Workshop, 2005

21. Physical Mechanisms of Ultra-thin Silicon Dioxide Degradation and Breakdown
E. M. Vogel
Electrochemical Society Meeting, 2005. *invited

22. Comparison of scanning capacitance microscopy and scanning Kelvin probe microscopy in determining two-dimensional doping profiles of Si homostructures
S.-E. Park, N. V. Nguyen, J. J. Kopanski, J. S. Suehle, and E. M. Vogel,
Ultra Shallow Junction Conference, Daytona Beach, FL, 2005.

23. Characterization of electrically active defects in high-k gate dielectrics using charge pumping
E. M. Vogel and D. Heh
NATO Advanced Research Workshop on Defects in Advanced High-k Dielectric Nanoelectronic Semiconductor Devices, 2005.  *invited

24. Electrical Characterization of MOS structures and Wide Bandgap Semiconductors by Scanning Kelvin Probe Microscopy
S.-E. Park, St. Jeliazkov, J. J. Kopanski, J. Suehle, E. Vogel, A. Davydov, and H.-K. Shin
MRS Spring Meeting, San Francisco, CA, 2005.

25. Metrology for Emerging Research Devices and Materials
E. M. Vogel
Characterization and Metrology for ULSI Technology Conference, 2005. *invited

26. The Contribution of HfO2 Bulk Oxide Traps to Dynamic NBTI in pMOSFETs
B. Zhu, J. S. Suehle, E. Vogel, and J. B. Bernstein
IEEE International Reliability Physics Symposium, 2005.

27. A Perspective on the Future of Electronics
E. M. Vogel
Nano 2004, Baltimore, MD, Nov. 12, 2004. *invited

28. Reverse Short Channel Effects in High-k Gated nMOSFETs
J.-P. Han, S. M. Koo, E. M. Vogel, E. P. Gusev, C. D’Emic, C. A. Richter, and J. S. Suehle
13th Workshop on Dielectrics in Microelectronics, Kinsale, Ireland, June 28, 2004.

29. Characterization of Structural Quality of Bonded Silicon-on-Insulator Wafers by Spectroscopic Ellipsometry and Raman Spectroscopy
N. V. Nguyen, J. E. Maslar, J.-Y. Kim, J.-P. Han, J.-W. Park, D. Chandler-Horowitz , and E. M. Vogel
Materials Research Society Meeting, 2004.

30. New Insights into Threshold Voltage Shifts for Ultrathin Gate Oxides
D. Heh, E. M. Vogel, and J. B. Bernstein
IEEE Integrated Reliability Workshop, 2004.

31. Influence of Buffer Layer Thickness on the Ferroelectric Memory window of SrBi2Ta2O9/SiN/Si Structure
Jin-Ping Han, S.M. Koo, C. A. Richter and Eric Vogel,
16th international Symposium on Integrated Ferroelectrics (ISIF’04), Gyeongju, Korea, April 5-8, 2004.

32. Challenges of Electrical Measurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor Devices
E. M. Vogel, and G. A. Brown
International Conference on Characterization and Metrology for ULSI Technology, 2003. *invited

33. Thickness evaluation for 2 nm SiO2 films, a comparison of ellipsometric, capacitance-voltage and HRTEM measurements
J. Ehrstein, C. Richter, D. Chandler-Horowitz, E. Vogel, D. Ricks, C. Young, S. Spencer, S. Shah, D. Maher, B. Foran, A. Diebold, and P. Y. Hung
International Conference on Characterization and Metrology for ULSI Technology, 2003.

34. Characterization of ultrathin amorphous silicon and correlation with crystalline evolution after thermal annealing
J. Park, C. A. Richter, J. Y. Kim, N. V. Nguyen, J. E. Bonevich, and E. M. Vogel
MRS Spring Meeting, 2003.

35. Energy Distribution of Interface Traps in High-k Gated MOSFETs
J.-P. Han, E. M. Vogel, E. P. Gusev, C. D'Emic, C. A. Richter, D. Heh, and J. Suehle
Symposium on VLSI Technology, 2003.

36. Defect Generation in Ultra-thin Oxide Over Large Fluence Ranges
D. Heh, J. B. Bernstein, and E. M. Vogel,
IEEE Integrated Reliability Workshop, 2002.

37. Issues with Electrical and Reliability Characterization of Advanced Gate Dielectrics,
E. M. Vogel
5th Topical Research Conference on Reliability, Austin, TX, Oct. 28, 2002. *invited

38. Relevance of injected hot holes on the breakdown of ultra-thin silicon-dioxide metal-semiconductor devices
D. Heh, E. M. Vogel, and J. Bernstein
American Physical Society Spring Meeting, Indianapolis, IN, March 21, 2002.

39. Issues with Electrical and Reliability Characterization of Advanced Gate Dielectrics
E. M. Vogel
Proceedings of the 12th Workshop on Dielectrics in Microelectronics, Grenoble, France, Nov. 20, 2002. *invited

40. Degradation and breakdown of ultra-thin silicon dioxide by electron and hole injection
E. M. Vogel,
IEEE Microelectronics Reliability and Qualification Workshop, Glendale, CA, Dec. 11, 2001. *invited

41. Interaction of Electrons with Defects Created by Hot Holes in Ultra-thin Silicon Dioxide
E. M. Vogel, D. Heh, B. Wang, C. E. Weintraub, J. S. Suehle, M. D. Edelstein, and J. B. Bernstein, 32nd IEEE Semiconductor Interface Specialists Conference, Washington D.C., Nov. 29, 2001.

42. Latent Reliability Degradation of Ultra-Thin Oxides After Heavy Ion and γ –ray Irradiation
B. Wang, J. S. Suehle, J. F. Conley, Jr., E. M. Vogel, C. E. Weintraub, A. H. Johnston, and J. B. Bernstein
IEEE Integrated Reliability Workshop, 2001.

43. Differences between Quantum-Mechanical Capacitance-Voltage Simulators
C. A. Richter, E. M. Vogel, A. M. Hodge, and A.R. Hefner,
International Conference on Simulation of Semiconductor Processes and Devices, Athens, Greece, Sept. 5-7, 2001.

44. Issues with the Electrical Characterization and Reliability of MOS Devices With Advanced Gate Dielectrics
E. M. Vogel
Materials Research Society Workshop on Dielectric Science & New Functionality in Device Physics for Crystalline Oxides on Semiconductors (COS), Chattanooga, TN, September 11, 2001. *invited

45. Reliability of Ultra-thin Silicon Dioxide Under Substrate Hot-electron, Substrate Hot-hole, and Tunneling Stress
E. M. Vogel, M. D. Edelstein, and J. S. Suehle
12th Insulating Films on Semiconductors Conference, Udine, Italy, June 20-23, 2001. *invited

46. Challenges of High-k Gate Dielectrics for Future MOS Devices
J. S. Suehle, E. M. Vogel, M. D. Edelstein, C. A. Richter, N. V. Nguyen, I. Levin, and D. L. Kaiser, H. Wu, and J. Bernstein
6th International Symposium on Plasma and Process-Induced Damage, Monterey, CA, May 13-15, 2001.

47. Degradation and Breakdown of Ultra-thin Silicon Dioxide Induced by Substrate Hot Hole Injection
E. M. Vogel and J. S. Suehle
31st IEEE Semiconductor Interface Specialists Conference, San Diego, CA, Dec. 7-9, 2000.

48. The Effect of Stress Interruption and Pulsed Bias Stress on Ultra-thin Gate Dielectric Reliability B. Wang, J. S. Suehle, E. M. Vogel, and J. B. Bernstein
IEEE International Integrated Reliability Workshop, 2000.

49. Issues in High-k Gate Dielectrics for Future MOS Devices
E. M. Vogel, M. D. Edelstein, C. A. Richter, N. V. Nguyen, I. Levin, D. L. Kaiser, H. Wu, and J. Bernstein
IEEE Microelectronics Reliability and Qualification Workshop, Glendale, CA, Oct. 31, 2000. *invited

50. The Effects of Ionizing Radiation on Wear-out and Reliability of Thin Gate Oxides
J. S. Suehle, T. Myers, M. Edelstein, E. M. Vogel, and J. F. Conley, Jr.,
IEEE Microelectronics Reliability and Qualification Workshop, Glendale, CA, Oct. 31, 2000.

51. High-k Gate Dielectric Reliability – Issues in Characterization, Physical Modeling, and Assessment
E. M. Vogel
Materials Research Society High-k Gate Dielectric Workshop, New Orleans, LA, June 1-2, 2000. *invited

52. Temperature Dependence of Soft Breakdown and Wear-Out in Sub 3 nm SiO2 Films
J. S. Suehle, E. M. Vogel, B. Wang, and J. B. Bernstein
IEEE International Reliability Physics Symposium, 2000.

53. Panel presentation on “Is technology scaling limited by oxide reliability?”
E. M. Vogel
International Reliability Physics Symposium, Apr. 13, 2000. *invited

54. Extraction of the Gate Oxide Thickness of N- and P-Channel MOSFETs Below 20 Å from the Substrate Current Resulting from Valence-Band Electron Tunneling
A. Shanware, J. P. Shiely, H. Z. Massoud, E. Vogel, K. Henson, A. Srivastava, C. Osburn, J. R. Hauser, and J. J. Wortman
International Electron Device Meeting, 1999.

55. Degradation of Ultra-thin SiO2 Under Combined Substrate Hot Electron and Tunneling Stress
E. M. Vogel, J. S. Suehle, M. D. Edelstein, B. Wang, Y. Chen, and J. B. Bernstein
30th IEEE Semiconductor Interface Specialists Conference, Charleston, SC, December 2-4, 1999.

56. Sheet and Line Resistance of Patterned SOI Surface Film CD Reference Materials as a Function of Substrate Bias
R. A. Allen, E. M. Vogel, L. W. Linholm, and M. W. Cresswell
IEEE International Conference on Microelectronic Test Structures, 1999.

57. In Situ Diffuse Reflectance Spectroscopy for Measurement and Control of III-V Molecular Beam Epitaxy
J. E. Guyer, W. F. Tseng, W. R Thurber, E. M. Vogel, D. A. Gajewski, and J. G. Pellegrino
Materials Research Society Fall Meeting, Boston, MA, Nov. 29 - Dec. 3, 1999.

58. Properties of N- and P-Channel MOSFETs with Ultrathin RTCVD Oxynitride Gate Dielectrics E. M. Vogel, and J. J. Wortman
Electrochemical Society Spring Meeting, Seattle, Washington, May 2-7, 1999. *invited

59. MOSFET Substrate Currents due to Valence-Band Tunneling in 15-35 Å
A. Shanware, H. Z. Massoud, E. Vogel, K. Henson, J. R. Hauser, and J. J. Wortman
29th IEEE Semiconductor Interface Specialists Conference, San Diego, CA, December 3-5, 1998.

60. Properties of n-Channel and p-Channel MOSFETs with Ultrathin Gate Dielectrics
E. M. Vogel, C. E. Weintraub, and J. J. Wortman
SRC TECHCON ’98, Las Vegas, NV, September 9-11, 1998.

61. Evaluation of 2.0 nm Grown and Deposited Dielectrics in 0.1 mm PMOSFETs
A. Srivastava, H. H. Heinisch, E. Vogel, C. Parker, C. M. Osburn, N. A. Masnari, J. J. Wortman, and J. R. Hauser
Materials Research Society Meeting, 1998.

62. E. M. Vogel, J. J. Wortman, and J. R. Hauser,
The Use of RTCVD Oxynitrides in Ultra-thin Gate Dielectric Stacks
28th IEEE Semiconductor Interface Specialists Conference, Charleston, SC, December 4-6, 1997.

63. Silicon oxynitride films formed by rapid thermal chemical vapor deposition for VLSI applications
E. M. Vogel, J. J. Wortman, P. K. McLarty, V. H. C. Watt, and B. Kirkpatrick
ECS Symposium on Silicon Nitride and Silicon Dioxide Thin Insulating Films, 1997.  *invited

64. Stacked RTCVD Oxide and Oxynitride Films for Ultrathin Gate Dielectrics
E. M. Vogel, W. K. Henson, P. K. McLarty, J. J. Wortman, and J. R. Hauser,
27th IEEE Semiconductor Interface Specialists Conference, San Diego, CA, December 5-7, 1996.

65. A self-consistent physical explanation for the mobility behavior of n-channel and p-channel MOSFETs with oxynitride gate dielectrics formed by low pressure rapid thermal chemical vapor deposition
E. M. Vogel, W. L. Hill, V. Misra, P. K. McLarty, J. J. Wortman, J. R. Hauser, P. Morfouli, G. Ghibaudo, and T. Ouisse
26th IEEE Semiconductor Interface Specialists Conference, Charleston, SC, December 7-9, 1995.

66. Electrical and Reliability Properties of Thin Silicon Oxynitride Dielectrics Formed by Low Pressure Rapid Thermal Chemical Vapor Deposition
P. Morfouli, G. Ghibaudo, E. M. Vogel, W. L. Hill, V. M. Misra, P. K. McLarty, and J. J. Wortman
Proceedings of the 7th ESPRIT Workshop on Dielectrics in Microelectronics, Crete, Greece, November, 1995.

67. Noise Analysis of MOSFET’s with Ultra Thin Silicon Oxynitride Films Prepared by Low Pressure Rapid Thermal Chemical Vapor Deposition (LPRTCVD)
P. Morfouli, G. Ghibaudo, T. Ouisse, E. M. Vogel, W. L. Hill, V.  Misra, P. McLarty, J. J. Wortman
Proceedings of the 25th European Solid State Device Research Conference, Hague, Netherlands, September 25-27, 1995.

Industry/University Colloquia (*14 invited)
1. Electrical and Physical Properties of High-k Gate Dielectrics on III-V Semiconductors
E. M. Vogel
IBM TJ Watson Research Center, Physical Sciences Seminar, Oct. 24, 2008.  *invited

2. Biosensing Using Semiconductor Technologies
W. Hu, E. M. Vogel, J. Gao, and B. Sumer
IEEE-Dallas Chapter of Engineering in Medicine and Biology Society (EMBS), Feb. 19, 2007.  *invited

3. Initiatives in Nanometrology
E. M. Vogel and W. Hu
Texas Instruments, Dallas, TX, Jan. 8, 2007. *invited

4. Method for Measuring the Barrier Height at the High-k/Metal Electrode Interface, and Combinatorial Determination of Optimal Metal Gate Electrodes
M. Green and E. M. Vogel
SEMATECH Advanced Gate Stack Engineering Working Group Biannual Meeting, Austin, TX, Feb. 14, 2005.  *invited

5. Depth Profiles of Electrically Active Defects in High-k Gate Stacks Using Charge Pumping
E. M. Vogel and D. Heh
SEMATECH Advanced Gate Stack Engineering Working Group Biannual Meeting, Austin, TX, Feb. 15, 2005.  *invited

6. Characterization Needs for Emerging Research Materials and Devices
Eric M. Vogel
ITRS Emerging Research Materials Workshop, San Francisco, CA, July 11, 2004.  *invited

7. Computational Needs for Emerging Materials: An Experimental Metrologist's Viewpoint
Curt A. Richter and Eric Vogel
Materials Modeling for Emerging Research Materials Workshop, Austin, TX, June 7, 2004.  *invited

8. Challenges of Electrical Measurements of Advanced Gate Dielectrics in MOS Devices
E. M. Vogel
Applied Materials, Feb. 9, 2004.  *invited

9. NIST Response to ITRS and Beyond
E. M. Vogel and D. Blackburn
SRC Metrology Needs for Emerging Technologies Workshop, Raleigh, NC, May 3, 2002.  *invited

10. Reliability of Ultra-thin Silicon Dioxide for Future MOS Devices
E. M. Vogel
Penn State University, Dept. of Engineering Science, Oct. 4, 2000.  *invited

11. Capacitance and Conductance Characterization of MOS Capacitors with Tunneling Gate Dielectrics
Eric M. Vogel
SEMATECH Gate Stack Engineering Working Group Meeting, Raleigh, NC, November 11, 1999.  *invited

12. Electrical Characterization and Reliability of MOS Devices with Tunneling Gate Dielectrics
E. M. Vogel
IBM, Yorktown Heights, NY, October 14, 1999.  *invited

13. Alternate Dielectric Technology and Metrology
E. M. Vogel
University of Delaware, Dept. of Electrical and Computer Engineering, July 13, 1999.  *invited

14. Reliability of Ultrathin Oxides for MOS Devices
E. M. Vogel
North Carolina State University, Dept. of Electrical and Computer Engineering, Apr. 22, 1999.  *invited