Book Chapters
3. C. R. Cleavelin, L. Columbo, H. Niimi, S. Pas, and E. M. Vogel, “Oxidation and Gate Dielectrics” to appear in Handbook of Semiconductor Manufacturing Technology, vol. 2, Y. Nishi and R. Doering, Editors, CRC Press (2007).
2. E. M. Vogel, and V. Misra, ‘MOS Device Characterization,’ in Handbook of Silicon Semiconductor Metrology, Marcel-Dekker, ed. A. C. Diebold, pp. 59-96, 2001. Link
1. C. R. Cleavelin, S. Pas, E. M. Vogel, and J. J. Wortman, ‘Oxidation,’ in Handbook of Semiconductor Manufacturing Technology, CRC Press, ed. Y. Nishi, and R. Doering, 2000. Link
Journal Publications (*Invited)
43. D. Heh, C. D. Young, G. A. Brown, P. Y. Hung, A. Diebold, E. M. Vogel, J. B. Bernstein, and G. Bersuker,, “Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack,” IEEE Transactions on Electron Devices, vol. 54, 1338-1345, 2007. Link
42. Q. Li, S.-M. Koo, C. A. Richter, M. D. Edelstein, J. E. Bonevich, J. J. Kopanski, J. S. Suehle, and E. M. Vogel, “Precise alignment of single nanowires and fabrication of nanoelectromechanical switch and other test structures,” IEEE Transactions on Nanotechnology, vol. 6, pp. 256-263, 2007. Link
*41. E. M. Vogel, “Technology and metrology of new electronic materials and devices,” Nature Nanotechnology, vol. 2, pp. 25-32, 2007. Link
*40. C. M. Garner, and E. M. Vogel, “Metrology Challenges for Emerging Research Devices and Materials,” IEEE Transactions on Semiconductor Manufacturing, vol. 19, pp. 397-403, 2006. Link
39. K.-S. Chang, M. Green, J. Suehle, E. Vogel, H. Xiong, J. Hattrick-Simpers, I. Takeuchi, O. Famodu, K. Ohmori, P. Ahmet, T. Chikyow, P. Majhi, B.-H. Lee, and M. Gardner, “Combinatorial Study of Ni-Ti-Pt Ternary Metal Gate Electrodes on HfO2 for the Advanced Gate Stack,” Applied Physics Letters, vol. 89, art no. 142108, 2006. Link
38. C. A. Richter, C. A. Hacker, L. J. Richter, O. A. Kirillov, J. S. Suehle, and E. M. Vogel, “Interface Characterization of Molecular-Monolayer/SiO2 Based Molecular Junctions,” Solid-State Electronics, vol. 50, pp. 1088-1096, 2006. Link
37. D. Heh, E. M. Vogel, J. B. Bernstein, C. D. Young, G. A. Brown, P. Y. Hung, and A. Diebold, G. Bersuker, “Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stacks,” Applied Physics Letters, vol. 88, art no. 152907, 2006. Link
36. S.-E. Park, N. V. Nguyen, J. J. Kopanski, J. S. Suehle, and E. M. Vogel, “Comparison of scanning capacitance microscopy and scanning Kelvin probe microscopy in determining two-dimensional doping profiles of Si homostructures,” Journal of Vacuum Science and Technology B, vol. 24, pp. 404-407, 2006. Link
35. J. Ehrstein, C. Richter, D. Chandler-Horowitz, E. Vogel, C. Young, S. Shah, D. Maher, B. Foran, P. Y. Hung, and A. Diebold, “A Comparison of Thickness Values for Very Thin SiO2 Films by Using Ellipsometric, Capacitance-Voltage, and HRTEM Measurements,” Journal of the Electrochemical Society, vol. 153, pp. F12-F19, 2006. Link
34. S.-M. Koo, Q. Li, M. D. Edelstein, C. A. Richter, and E. M. Vogel,
“Enhanced Channel Modulation in Dual-Gated Silicon Nanowire Transistors,” NanoLetters, vol. 5, pp. 2519-2523, 2005. Link
33. S.-M. Koo, M. D. Edelstein, Q. Li, C. A. Richter, and E. M. Vogel, “Silicon nanowires as enhancement-mode Schottky-barrier field-effect transistors,” Nanotechnology, vol. 16, pp. 1482-1485, 2005. Link
32. G. K. Ramachandran, M. D. Edelstein, D. L. Blackburn, J. S. Suehle, E. M. Vogel, and C. A. Richter, “Nanometre gaps in gold wires are formed by thermal migration,” Nanotechnology, vol. 16, pp. 1294-1299, 2005. Link
31. J.-P. Han, S. M. Koo, E. M. Vogel, E. P. Gusev, C. D'Emic, C. A. Richter, and J. S. Suehle, ‘Reverse Short Channel Effects in High-k gated nMOSFETs,’ Microelectronics Reliability, vol. 45, pp. 783-785, 2005. Link
30. S.-M. Koo, A. Fujiwara, J.-P. Han, E. M. Vogel, C. A. Richter, and J. E. Bonevich, “High Inversion Current in Silicon Nanowire Field Effect Transistors,” NanoLetters, vol. 4, pp. 2197-2201, 2004. Link
29. N. V. Nguyen, J. E. Maslar, Jin-Yong Kim, Jin-Ping Han, Jin-Won Park, D. Chandler-Horowitz, and E. M. Vogel, “Crystalline Quality of Silicon-On-Insulator Characterized by Spectroscopic Ellipsometry and Raman Spectroscopy,” Applied Physics Letters, vol. 85, pp. 2765-2767, 2004. Link
28. J.-P. Han, S.-M. Koo, C. A. Richter, and E. M. Vogel, “Influence of buffer layer thickness on memory effects of SrBi2Ta2O9/SiN/Si structures”, Applied Physics Letters, vol. 85, pp. 1439-1441, 2004. Link
27. C. A. Richter, C. Hacker, L. J. Richter, E. M. Vogel, "Molecular Devices Formed by Direct Monolayer Attachment to Silicon", Solid-State Electronics, vol. 48, pp. 1747-1752, 2004. Link
26. J.-P. Han, E. M. Vogel, E. P. Gusev, C. D'Emic, C. A. Richter, D. W. Heh, and J. S. Suehle, "Asymmetric Energy Distribution of Interface Traps in n- and p-MOSFETs with HfO2 Gate Dielectric on Ultrathin SiON Buffer Layer," IEEE Electron Device Letters, vol. 25, pp. 126-128, 2004. Link
25. E. M. Vogel, C. A. Richter, and B. G. Rennex, ‘A capacitance-voltage model for polysilicon-gated MOS devices including substrate quantization effects based on modification of the total semiconductor charge,’ Solid-State Electronics, vol. 47, pp. 1589-1596, 2003. Link
24. D.-W. Heh, E. M. Vogel, and J. B. Bernstein, ‘Impact of Substrate Hot Hole Injection on Ultra-thin Silicon Dioxide Breakdown,’ Applied Physics Letters, vol. 82, pp. 3242-3244, 2003. Link
23. E. M. Vogel, D.-W. Heh, and J. B. Bernstein, ‘Impact of the Trapping of Anode Hot Holes on Silicon Dioxide Breakdown,’ IEEE Electron Device Letters, vol. 23, pp. 667-669, 2002. Link
22. E. M. Vogel, D. Heh, and J. B. Bernstein, ‘Interaction between low energy electrons and defects created by hot holes in ultra-thin silicon dioxide,’ Applied Physics Letters, vol. 80, pp. 3343-3345, 2002. Link
21. J. S. Suehle, E. M. Vogel, P. Roitman, J. F. Conley, Jr., A. H. Johnston, B. Wang, J. B. Bernstein, and C. E. Weintraub, ‘Observation of Latent Reliability Degradation in Ultra-Thin Oxides After Heavy-Ion Irradiation,’ Applied Physics Letters, vol. 80, pp. 1282-1284, 2002. Link
20. J. F. Conley, Jr., J. S. Suehle, A. H. Johnston, B. Wang, T. Miyahara, E. M. Vogel, and J. B. Bernstein, ‘Heavy Ion Induced Soft Breakdown of Thin Gate Oxides,’ IEEE Transactions on Nuclear Science, vol. 48, pp. 1913-1916, 2001. Link
19. C. E. Weintraub, E. M. Vogel, N. Yang, V. Misra, J. J. Wortman, J. J. Ganem, and P. Masson, ‘Application of Low Frequency Charge Pumping on Thin Stacked Dielectrics,’ IEEE Transactions on Electron Devices, vol. 48, pp. 2754-2762, 2001. Link
18. E. M. Vogel, M. D. Edelstein, and J. S. Suehle, ‘Reliability of Ultra-thin Silicon Dioxide Under Substrate Hot-electron, Substrate Hot-hole, and Tunneling Stress,’ Microelectronic Engineering, vol. 59, pp. 73-83, 2001. Link
17. E. M. Vogel, M. D. Edelstein, and J. S. Suehle, ‘Defect generation and breakdown of ultra-thin silicon dioxide induced by substrate hot-hole injection,’ Journal of Applied Physics, vol. 90, pp. 2338-2346, 2001. Link
16. B. Wang, J. S. Suehle, E. M. Vogel, and J. B. Bernstein, ‘Time-Dependent Breakdown of Ultra-Thin SiO2 Gate Dielectrics Under Pulsed Biased Stress,’ IEEE Electron Device Letters, vol. 22, pp. 224-226, 2001. Link
15. C. A. Richter, A. R. Hefner, and E. M. Vogel, ‘A Comparison of Quantum-Mechanical Capacitance-Voltage Simulators,’ IEEE Electron Device Letters, vol. 22, pp. 35-37, 2001. Link
14. W. K. Henson, N. Yang, S. Kubicek, E. M. Vogel, J. J. Wortman, K. De Meyer, and
A. Naem, ‘Analysis of Leakage Currents and Power Consumption for CMOS Technology in the 100 nm Regime,’ IEEE Transactions on Electron Devices, vol. 47, pp.1393-1400, 2000. Link
13. E. M. Vogel, J. S. Suehle, M. D. Edelstein, B. Wang, Y. Chen, and J. B. Bernstein, ‘Reliability of Ultra-thin Silicon Dioxide Under Combined Substrate Hot Electron and Constant Voltage Tunneling Stress,’ IEEE Transactions on Electron Devices, vol. 47, pp. 1183-1191, 2000. Link
12. E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, ‘Limitations of Conductance to the Measurement of the Interface State Density of MOS Capacitors with Tunneling Gate Dielectrics,’ IEEE Transactions on Electron Devices, vol. 47, pp. 601-608, 2000. Link
11. A. Shanware, H. Z. Massoud, E. Vogel, K. Henson, J. R. Hauser, and J. J. Wortman, ‘Modeling the Trends in Valence-Band Electron Tunneling in NMOSFETs with Ultrathin SiO2 and SiO2/Ta2O5 Dielectrics with Oxide Scaling,’ Microelectronic Engineering, vol. 48, pp. 295-298, 1999. Link
10. P. Masson, P. Morfouli, J. L. Autran, J. Brini, B. Balland, E. M. Vogel, and J. J. Wortman, ‘Electrical Properties of Oxynitride Thin Films Using Noise and Charge Pumping Measurements,’ Journal of Non-Crystalline Solids, vol. 245, pp. 54-58, 1999. Link
9. W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. Dätta, M. Xu and D. Venables, ‘Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors,’ IEEE Electron Device Letters, vol. 20, pp. 179-181, 1999. Link
8. V. Z-Q. Li, M. R. Mirabedini, E. Vogel, K. Henson, D. Batchelor, J. J. Wortman, and R. T. Kuehn, ‘Effects of Si Source Gases (SiH4 and Si2H6) on Polycrystalline-Si1-xGex Deposited on Oxide by RTCVD,’ Electrochemical and Solid-State Letters, vol. 1, pp. 153-155, 1998. Link
7. E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Henson, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. J. Wortman, ‘Modeled tunnel currents for high dielectric constant dielectrics,’ IEEE Transactions on Electron Devices, vol. 45, pp.1350-1355, 1998. Link
6. P. Morfouli, G. Ghibaudo, E. M. Vogel, W. L. Hill, V. Misra, P. K. McLarty, and J. J. Wortman, ‘Electrical and reliability properties of thin silicon oxynitride dielectrics formed by low pressure rapid thermal chemical vapor deposition’ Solid-State Electronics, vol. 41, pp. 1051-1055, 1997. Link
5. P. Morfouli, G. Ghibaudo, T. Ouisse, E. Vogel, W. Hill, V. Misra, P. McLarty, and J. J. Wortman, ‘Low-frequency noise characterization of n- and p- MOSFET’s with ultrathin oxynitride gate films,’ IEEE Electron Device Letters, vol. 17, pp. 395-397, 1996. Link
4. E. M. Vogel, W. L. Hill, V. Misra, P. K. McLarty, J. J. Wortman, J. R. Hauser, P. Morfouli, G. Ghibaudo, and T. Ouisse, ‘Mobility behavior of n-channel and p-channel MOSFETs with oxynitride gate dielectrics formed by low-pressure rapid thermal chemical vapor deposition,’ IEEE Transactions on Electron Devices, vol. 43, pp. 753-758, 1996. Link
3. V. Misra, W. K. Henson, E. M. Vogel, G. A. Hames, P. K. McLarty, J. R. Hauser, and J. J. Wortman, ‘Electrical properties of composite gate oxides formed by rapid thermal processing,’ IEEE Transactions on Electron Devices, vol. 43, pp. 636-646, 1996. Link
2. W. L. Hill, E. M. Vogel, V. Misra, P. K. McLarty, and J. J. Wortman, ‘Low-pressure rapid thermal chemical vapor deposition of oxynitride gate dielectrics for n-channel and p-channel MOSFETs,’ IEEE Transactions on Electron Devices, vol. 43, pp. 15-22, 1996. Link
1. W. L. Hill, E. M. Vogel, P. K. McLarty, V. Misra, J. J. Wortman, and V. Watt, ‘N-channel and p-channel MOSFETs with gate dielectrics formed using low pressure rapid thermal chemical vapor deposition,’ Microelectronic Engineering, vol. 28, pp. 269-272, 1995. Link
Conference Proceedings (*Invited)
20. C. D. Young, S. Nadkarni, D. Heh, H. R. Harris, R. Choi, J. J. Peterson, J. H. Sim, S. A. Krishnan, J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G. A. Brown, and G. Bersuker, “Detection of Electron Trap Generation Due to Constant Voltage Stress on High-κ Gate Stacks,” IEEE International Reliability Physics Symposium Proceedings, pp. 169-173, 2006. Link
19. C. D. Young, S. Nadkarni, D. Heh, H. R. Harris, R. Choi, J. J. Peterson, J. H. Sim, S. A. Krishnan, J. Barnett, E. Vogel, B.H. Lee, P. Zeitzoff, G. A. Brown, and G. Bersuker, “Detection of trap generation in high-kappa gate stacks,” IEEE Integrated Reliability Workshop Final Report, pp. 79-83, 2005. Link
18. H. D. Xiong, N. V. Nguyen, J. J. Kopanski, J. S. Suehle, and E. M. Vogel, “Work function characterization of TaSiN and TaCN electrodes using CV, IV, IPE and SKPM,” ECS Transactions, vol. 3, pp. 25-36, 2006. Link
*17. E. M. Vogel, D. Heh, “Characterization of electrically active defects in high-k gate dielectrics using charge pumping,” in NATO Advanced Research Workshop on Defects in Advanced High-k Dielectric Nanoelectronic Semiconductor Devices, pp. 85-96, 2005.
*16. E. M. Vogel, “Physical Mechanisms of Ultra-thin Silicon Dioxide Degradation and Breakdown,” Proceedings of the Electrochemical Society PV 2005-01, pp. 279-292, 2005. Link
15. B. Zhu, J. S. Suehle, E. Vogel, and J. B. Bernstein, “The Contribution of HfO2 Bulk Oxide Traps to Dynamic NBTI in pMOSFETs,” IEEE International Reliability Physics Symposium Proceedings, pp. 533-537, 2005. Link
*14. E. M. Vogel, “Metrology for Emerging Research Devices and Materials,” in Characterization and Metrology for ULSI Technology, AIP Conference Proceedings, vol. 788, pp. 650-655, 2005.
13. N. V. Nguyen, J. E. Maslar, J.-Y. Kim, J.-P. Han, J.-W. Park, D. Chandler-Horowitz , and E. M. Vogel, “Characterization of Structural Quality of Bonded Silicon-on-Insulator Wafers by Spectroscopic Ellipsometry and Raman Spectroscopy,” in Materials Research Society Spring Meeting, High-Mobility Group-IV Materials and Devices, pp. 127-132, 2004.
12. D. Heh, E. M. Vogel, and J. B. Bernstein, “New Insights into Threshold Voltage Shifts for Ultrathin Gate Oxides,” IEEE Integrated Reliability Workshop Final Report, pp. 99-101, 2004. Link
11. J.-P. Han, E. M. Vogel, E.P. Gusev, C. D'Emic, C.A. Richter, D. W. Heh, J. Suehle, “Energy Distribution of Interface Traps in High-k Gated MOSFETs,” Digest of Technical Papers - Symposium on VLSI Technology, pp. 161-162, 2003. Link
*10. E. M. Vogel, and G. A. Brown, “Challenges of Electrical Measurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor Devices,” in International Conference on Characterization and Metrology for ULSI Technology, AIP Conference Proceedings, vol. 683, pp. 771-781, 2003.
9. J. Ehrstein, C. Richter, D. Chandler-Horowitz, E. Vogel, D. Ricks, C. Young, S. Spencer, S. Shah, D. Maher, B. Foran, A. Diebold, and P. Y. Hung, “Thickness evaluation for 2 nm SiO2 films, a comparison of ellipsometric, capacitance-voltage and HRTEM measurements,” in International Conference on Characterization and Metrology for ULSI Technology, AIP Conference Proceedings, vol. 683, pp. 331-336, 2003.
8. D. Heh, J. B. Bernstein, E. M. Vogel, “Defect Generation in Ultra-thin Oxide Over Large Fluence Ranges,” IEEE Integrated Reliability Workshop Final Report, pp. 9-13, 2002. Link
7. B. Wang, J. S. Suehle, J. F. Conley, Jr., E. M. Vogel, C. E. Weintraub, A. H. Johnston, and J. B. Bernstein, “Latent Reliability Degradation of Ultra-Thin Oxides After Heavy Ion and γ –ray Irradiation,” IEEE Integrated Reliability Workshop Final Report, pp. 16-19, 2001. Link
6. B. Wang, J. S. Suehle, E. M. Vogel, and J. B. Bernstein, “The Effect of Stress Interruption and Pulsed Bias Stress on Ultra-thin Gate Dielectric Reliability,” IEEE International Integrated Reliability Workshop Final Report, pp. 74-79, 2000. Link
5. J. S. Suehle, E. M. Vogel, B. Wang, J. B. Bernstein, “Temperature Dependence of Soft Breakdown and Wear-Out in Sub 3 nm SiO2 Films,” IEEE International Reliability Physics Symposium Proceedings, pp. 33-39, 2000. Link
4. A. Shanware, J. P. Shiely, H. Z. Massoud, E. Vogel, K. Henson, A. Srivastava, C. Osburn, J. R. Hauser, and J. J. Wortman, “Extraction of the Gate Oxide Thickness of N- and P-Channel MOSFETs Below 20 Å from the Substrate Current Resulting from Valence-Band Electron Tunneling,” Technical Digest - International Electron Device Meeting, pp. 815-819, 1999. Link
3. R. A. Allen, E. M. Vogel, L. W. Linholm, and M. W. Cresswell, “Sheet and Line Resistance of Patterned SOI Surface Film CD Reference Materials as a Function of Substrate Bias,” IEEE International Conference on Microelectronic Test Structures, pp. 51-55, 1999. Link
2. A. Srivastava, H. H. Heinisch, E. Vogel, C. Parker, C. M. Osburn, N. A. Masnari, J. J. Wortman, and J. R. Hauser, “Evaluation of 2.0 nm Grown and Deposited Dielectrics in 0.1 mm PMOSFETs,” Materials Research Society Symposium - Proceedings, vol. 525, pp. 163-170, 1998.
*1. E. M. Vogel, J. J. Wortman, P. K. McLarty, V. H. C. Watt, and B. Kirkpatrick, “Silicon oxynitride films formed by rapid thermal chemical vapor deposition for VLSI applications,” Proceedings of the Symposium on Silicon Nitride and Silicon Dioxide Thin Insulating Films, vol. 97, pp. 394-407, 1997.