Wednesday,
November 22, 2017

Wednesday,
November 22, 2017

Category:

Engineer Gets Grant to Boost Security in Computer Chip Production

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Dr. Jeyavijayan Rajendran

Since the early 2000s, the semiconductor industry has been steadily increasing the amount of computer chips it produces in outsourced plants, leading to production security concerns that researchers at UT Dallas are working to address.

Dr. Jeyavijayan Rajendran, an assistant professor of electrical engineering in the Erik Jonsson School of Engineering and Computer Science, his research team and researchers at Texas A&M University have received a $480,000 grant to develop new techniques in the physical design of integrated circuits to improve the security of a method known as split manufacturing. The grant is jointly funded by the National Science Foundation and the Semiconductor Research Corporation.

Rajendran, who is also affiliated with the computer engineering program, said the growing trend in outsourcing — where companies relay some aspect of the fabrication, test or assembly to an offshore foundry — creates vulnerabilities to reverse-engineered attacks, counterfeiting and intellectual property piracy.

With split manufacturing, companies can divide the process into different production lines, alleviating some of the security concerns by hiding critical design information from an untrusted foundry — and any potential attackers within it.

“In the split-manufacturing framework, a design house creates the Front End of Line (FEOL) layers at an untrusted, high-end foundry,” Rajendran said. “The Back End of Line (BEOL) layers are then fabricated at the design house’s trusted, low-end foundry. This allows companies to simultaneously alleviate the cost of owning a trusted foundry and eliminate the security risks associated with outsourcing the fabrication of integrated circuits.”

When designing a chip, manufacturers use automation tools that work in a reliable and predictable way to simplify production. For example, if two wires need to be connected, these automation tools will try to place the wires close to each other to make the design faster and transmit bits with less energy.

By separating the manufacturing process, companies can hide BEOL connections from potential attackers in the FEOL foundry, preventing them from exploiting the techniques used to secure the production.

But attackers can still use these automated processes to their advantage. They can build the missing parts of a chip’s design by identifying missing connections from the information available on their production line. Companies relying on inadequate security enhancements to the chip’s design overlook these vulnerabilities, and they can incur significant costs and lost time, Rajendran said.

There are different types of attacks that can take place. If I’m an attacker at a foundry, I can insert hardware Trojans into the product, which make malicious modifications to the design. I can use these tools to leak secret information or modify regular functionality. Think of it as regular software, except hardware attacks can do much more damage.

Dr. Jeyavijayan Rajendran, assistant professor of electrical engineering in the Erik Jonsson School of Engineering and Computer Science

The research team is working to mimic potential attacks by developing models that can determine a design’s missing connections, just as an attacker would with the limited design information given to the untrusted foundry. Rajendran is planning to set up a competition among his students, challenging them to find possible attacks. He hopes to expand the effort to similar research teams across the country.

“There are different types of attacks that can take place,” Rajendran said. “If I’m an attacker at a foundry, I can insert hardware Trojans into the product, which make malicious modifications to the design. I can use these tools to leak secret information or modify regular functionality. Think of it as regular software, except hardware attacks can do much more damage.”

Attackers also can take advantage of this process to create unauthorized chips. Foundries that receive an order with the chip design first make a mask that acts as the mold with which multiple chips can be made, Rajendran said. Once the authentic order is fulfilled, an attacker can continue to make additional chips, usually for sale on the black market. 

Once the team has developed systematic techniques for addressing these attacks, it can modify the physical design of the integrated circuit by changing the structure of the chip gates.

“To overcome this security vulnerability in split manufacturing, we developed an automated tool that ensures security by design,” he said. “This defense improves the security of split manufacturing by deceiving the FEOL attacker into making wrong connections.”

Media Contact: Miguel Perez, 972-883-2207, [email protected]
or the Office of Media Relations, 972-883-2155, [email protected].


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