Aditya Awasthi
Education
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Indian Institute of Technology, Kanpur
B. Tech. (Electrical Engineering), graduated in 2004, CPI - 8.1/10
University of Texas at Dallas
M.S.(EE - Circuits and Systems), since fall 2006, GPA - 4.0
Employment History
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Eric Jonsson Distinguished Research Assistant
University of Texas at Dallas
14th August, 2006 - till date
Description:
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Advisor - Professor Poras T. Balsara
Research interests - Circuits and Communication.
Component Design Engineer
Intel, Bangalore
6th March, 2006 - 4th July, 2006
Description:
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Worked in "LTG/DAC" team of Mobility Group at Intel, India. I was responsible for Synopsys/Magma based flow development and resolving issues faced by design teams at various technology nodes.
Completed Projects:
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· Design Margin Estimation and Implementation for Magma/PT based ASIC design flow for TSMC-130nm. This involved Monte Carlo simulations based yield analysis and detailed understanding of process variations and standard cell library characterization.
· Fully validated TSMC-130nm backend flow (magma based)
Design Engineer
Texas Instruments, Bangalore
12th July, 2004 - 3rd March, 2006
Description:- Worked in "Platforms/Sub-Systems" group of Wireless Division at Texas Instruments, India. I was responsible for Logical and Physical Synthesis and STA of the design.
· Core Familiarity: ARM9, ARM11
· Products released-
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ETM9: ARM926 based chip on 90nm technology (used in full-chip OMAP).
L220: ARM1176 based level-2 cache controller on 65nm process technology
GFX: Imagination Tech. (MBX) based 3D-Graphics module on 65nm node.
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1. Integration Specification, Timing Constraints, and Power Management Specification
2. Logical and physical synthesis (includes placement, floorplan, clock expansion and routing) and STA sign-off (with normal and coupled spef)
3. Implementation of 5000x power management which include Switch-Cells/Isolation Latches, Retention-Flops, Memory-retention, Clock-Gating, and SmartReflexTM (Dynamic Voltage and Frequency Scaling).
Patents, Publications and Technical Reports
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1. A. Iyer, Z. Parker, A. Awasthi. "Master Slave Pre-Charge Flip-Flop (MSPCFF)", filed for US patent - Docket No. TI-61597
2. C. Rajan, A. Awasthi, and A. G. Bhujle. "Modeling and simulation of Magnetic Pulse Compression circuit for high average power N2 - laser", Proceedings of National Laser Symposium - 2002, pp - 173.
3. A. Saxena, A. Awasthi, and V. Vaish. SANKET: Hand Gesture Recognition, submitted for IEEE CSIDC 2003.
4. A. Awasthi and P. Kishore. "DFT Friendly Synthesis", submitted for 10X-productivity efforts, Texas Instruments, India.
5. A. Awasthi. "Physical design flow: Timing convergence between logical and physical domain", submitted as white paper, Texas Instruments, India
Research Experience
· Texas Instruments, Bangalore, India. From July, 2004
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Designed a high performance flip-flop with superior BHT (>100ps) with respect to the existing fast flop architectures in TI. The architecture is robust across all PTVs and is more resistant to Cross talk/other random parasitic effects.
Developed synthesis flow that confronts issues arising from DFT domain during synthesis (and STA), early in the design flow and attempt to reduce DFT related design iterations.
Compared gain-based synthesis (Magma) with wire-load model based synthesis (Synopsys) using data from L220 sub-chip developed in TI. Key areas were area, timing, execution-time and adaptability to the upcoming process-technology.
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Developed model of MEMS based Electrostatic Comb Actuators for simulation. These incorporated manufacturing-process parameters, physical description of the comb structure and interaction with environment (e.g. Force exerted, Voltage applied and Levitation effects). Demonstrated a possible application of comb-drives as mechanical-memory.
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Developed a real-time hand gesture recognition system to provide a alternate means of input to computer by hand gestures.
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Developed an Average Current-Mode (ACM) control based, cascaded four-stage programmable switch-mode power supply to be used for excitation of a multi-kilowatt, transverse flow, CW CO2 laser.
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Developed models of electric discharge in pulsed laser and of magnetic cores, for spice simulation of Magnetic Pulse Compression Circuit.
Awards and Honors
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1. Jonsson School Distinguished Assistantship, University of Texas at Dallas, 2006
2. Spontaneous Recognition Award, Intel, 2006
3. Nominated for best B.Tech thesis in the EE department at IIT Kanpur, 2004
4. Best seminar and project, in Young Scientist Research Program, held at Centre for Advanced Technology, Indore, 2002
5. Merit Scholarship (4-year tuition waiver and stipend) by IIT Kanpur to pursue undergraduate studies.
6. Scholarship and Certificate of merit awarded by the Central Board of Secondary Education, for being among the top 0.1% of the successful candidates {Mathematics}, in the All India Secondary Examination, 1997
Software Exposure
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EDA:
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· Synopsys: Design Compiler, Physical Compiler, Prime Time, Formality
· Magma: Mantle based flows- BlastCreate {Synthesis}, BlastFusion {STA}
· Cadence: Analog Design Environment
· Spice, Matlab
Programming Languages:
- Verilog, VHDL, C/C++, Perl, Tcl & Awk
Operating Systems:
- Linux/Solaris, Windows
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· Organizations: IEEE, National Scholars Honor Society
· Member of IIT Kanpur Counseling Service: This body has been constituted to cater to the academic, psycho-emotional problems of the student community.
· Student Guide, Counseling Service, 2000-2001: To help six new fresher familiarize and acclimatize at IIT.
· Held position of Coordinator and Secretary in IIT Kanpur Cultural Festivals.
· Member of PRAYAS, a student organization for imparting education to poor children near IIT Kanpur campus and nearby villages.
· Participated in various software and electronic competitions at IIT Kanpur.