Course Outline

Fall 2012

Professor C. D. Cantrell, UT-Dallas

Textbook

Computer Organization and Design, Fourth Edition, Revised Printing, by David Patterson and John Hennessy (Morgan Kaufmann Publishers, 2011). (Required) Please DO NOT buy a copy of a previous edition.

Target audiences:

• This is a required core course for degree-seeking undergraduate students in Computer Engineering, and is a required prerequisite for CE/EE 6304, Computer Architecture.
• An understanding of the material in this course is strongly recommended for all students who intend to take EE 6381, Computational Methods in Engineering.
• Others who can benefit from this course include employees of local high-technology companies who need an introduction to computer architecture.

Concepts/tools to be acquired in this course:

Overall goals of CE/EE 4304:

• Acquire the ability to use a hierarchical (layered) approach to understand a complex digital system
  • Hardware
  • Software
  • This ability is useful in many CE/EE courses and on the job
• Become sufficiently well acquainted with the principles of computer architecture to be able to make intelligent use of computers for designing and simulating engineering systems, components, and devices

Specific concepts and tools:

1. Performance measurement and comparison
   • Possible definitions of performance
     • Execution time
     • Operations per second
     • Throughput (e.g., transactions per hour)
     • Real-time computing and performance metrics
   • Metrics for processor performance
     • Formula for execution time
     • Wall-clock (elapsed) time vs. user CPU time + system time
     • MIPS
     • MFLOPS (maximum vs. actual)
     • Linpack
   • Relating the metrics
   • The SPEC performance metrics
   • Choosing benchmark programs to evaluate processor performance
   • Comparing and summarizing performance
2. Data representations
   • Data types supported in RISC architectures
   • Floating-point representations
     • Motivation, concepts and base-10 examples
     • IEEE-754 single precision
       • Conversion between decimal and IEEE-754 s.p. representations
     • IEEE-754 double precision
     • TI DSP floating-point representations
       • Conversion between decimal and TI-DSP representations
     • Features of floating-point representations
       • Smallest representable positive number
       • Largest representable positive number
       • NaNs and denormalized numbers
3. Computer arithmetic
   • Integer addition and subtraction
     • Integer overflow
   • Logical operations
   • Integer multiplication
   • Computational aspects of the IEEE-754 floating-point representations
     • Floating-point overflow and underflow
     • Machine epsilon
     • Consecutive floating-point numbers near 1.0
       • Wobble
     • Rounding
       • Bias in consistently rounding up or down
       • Round to nearest (or round to even in case of a tie)
     • Catastrophic cancellation of significant digits in subtraction
       • Examples
         • Evaluation of a polynomial
         • Evaluation of the sine of a large angle
     • Ill-conditioned problems
       • Example: Finding multiple roots of a polynomial
4. Design of the datapath and control of a processor that executes a subset of the full MIPS instruction set
   • Design of the datapath of an ALU that executes the add, sub, and, or, and slt instructions
   • Control signals for the ALU
   • State elements and clocking
   • Block view of a single-clock-cycle processor datapath
   • Control of the single-clock-cycle implementation
   • Performance analysis of the single-clock-cycle implementation
   • A simple multiple-clock-cycle processor datapath
   • Control of the multiple-clock-cycle implementation
     • State diagram
     • Implementation of state transitions using microprogrammed control
   • Exceptions and interrupts
     • Exception handling in 80x86 architecture and DOS operating system
     • Exception handling in RISC architectures and UNIX operating system
5. Pipelining
   • A pipelined datapath
   • Pipelined control
   • Visualization of pipelined data flow
     • Pipeline diagrams
     • Gantt charts
   • Examples
   • Data hazards
     • Compiler elminiation of data hazards
     • Hardware control for data hazards: Stalls
     • Reducing data hazards: Forwarding
   • Branch hazards
   • Performance of pipelined systems
   • Programming for a pipelined processor in a higher-level language
6. Overview of memory system technology and architecture
   • Hardware implementations of 1-bit memory
     • DRAM
     • SRAM
     • ROM
   • Hardware implementations of multiple-bit memory
     • DRAM
     • SRAM
     • ROM
   • SRAM and DRAM chip and system architectures
   • System bus architectures (processor to/from memory)
7. Hierarchical memory systems
   • The processor-memory speed gap
   • Interleaved memory
   • Caches
     • Direct-mapped caches
     • Fully associative caches
     • Set-associative caches
     • Examples
       • Level 1 caches
       • Level 2 caches
   • Virtual memory
   • A common framework for memory hierarchies
   • Programming for hierarchical memory in a higher-level language
8. Interfacing processors and peripheral devices
   • I/O Performance measures: Some examples from disk and file systems
   • Types and characteristics of I/O devices
   • Buses: Connecting I/O devices to processor and memory
   • Interfacing I/O devices to the memory, processor and operating system
9. Parallel processors
   • SIMD computers--Single Instruction Stream, Multiple Data Streams
   • MIMD Computers--Multiple Instruction Streams, Multiple Data Streams
   • Programming MIMDs
   • MIMDs connected by a single bus
   • MIMDs connected by a network
   • Future directions for parallel processors
   • Programming for parallel processors in a higher-level language

Background

CE/EE 4304 is a junior/senior required core course for Computer Engineering majors. CE/EE 4304 provides a systematic introduction to computer architecture, and is a prerequisite for the graduate computer architecture course, CE/EE 6304. CE/EE 4304 is neither a digital circuits course nor an assembly language course, but it uses digital circuit concepts, assembly language, and other tools as part of a systematic investigation of modern approaches to computer architecture.

The textbook is Computer Organization and Design: The Hardware-Software Interface, Revised Fourth Edition, by Professors David A. Patterson and John L. Hennessy.

Professors Patterson and Hennessy are the academic originators of RISC (Reduced Instruction Set Computer) architectures. Professor Hennessy designed the first of the MIPS family of processors, which were used in computers manufactured by Silicon Graphics and are now used extensively in embedded systems such as laser printers, Nintendo 64 and Sony PlayStation. Professor Patterson's RISC design underlies the SPARC family of processors used by Sun Microsystems and manufacturers of Sun-compatible computers. RISC design principles are used in many microprocessor families (including the Pentium, PowerPC, Alpha, SPARC, PA-RISC, Motorola 88000, and Intel i860/i960 families).

Topics covered in EE 4304 include CPU and I/O performance analysis, architectures of integer and floating-point arithmetic units, design of the control units of single-cycle and multiple-cycle processors, basic principles of pipelining, introduction to memory architectures, concurrent processing, architectures of digital signal processors, vector architectures, router architectures, and basic principles of I/O systems. MIPS assembly language, SPIM, and other tools are used extensively to illustrate the basic operations of a RISC processor.

The industrial originator of RISC processing was Seymour Cray, who used nearly all of the most important RISC concepts in the Control Data 6600 (1964) and 7600 (1968), and in the CRAY series of vector supercomputers. EE 4304 will survey the CRAY X/MP architecture, as well as modern vector architectures such as the PowerPC G4 architecture.

The prerequisites for CE/EE 4304 are CE/EE 2310, Computer Organization and Design, and CE/EE 3320/3120, Digital Circuits/Digital Circuits Laboratory. CE/EE 4304 will build on, not duplicate, the topics taught in the prerequisite courses. CE/EE 4304 will also assume that all students are completely familiar with integer data representations, and are able to write programs in MIPS assembly language and use the SPIM simulator. A reference document for MIPS assembly language is available.