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Publications

Journal Publications

Sameer Arora, Poras T Balsara, Dinesh K Bhatia, “Digital Pulse Width Modulation using Direct Digital Synthesis”, IEEE Transactions on Very Large Scale Integration Systems, submitted.

Sameer Arora, Poras T Balsara, Dinesh K Bhatia , “Passivity-Based Control For Direct Voltage Regulation For BOOST DC-DC Converter”, IET Power Electronics, submitted.

Sameer Arora, Poras T Balsara, Dinesh K Bhatia , “Input-Output Linearization of a Boost Converter with Mixed Load (Constant Voltage and Constant Power Load)”, IEEE Transaction on Power Electronics, to appear.

Sujan K. Manohar, Louis Hunt, Poras T. Balsara, Dinesh Bhatia, Vikas Paduvalli, “Minimum Phase Wide Output Ranga Digitally Controlled SIDO Boost Converter”, IEEE Transactions on Circuits and Systems-I, Vol. 62, Issue 9, pp. 2351-2360, August 2015.

William P. Walker and Dinesh Bhatia, “Automated Ingestion Detection for a Health Monitoring System”, IEEE Journal of Biomedical and Health Informatics, Vol. 18, Issue 2, pp. 682-692, March 2014.

Sanjay P. Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras Balsara, “Network Interface for NoC based Architecture” International Journal of Electronics, Volume 94, Issue 5, pp. 531-547, May 2007

Abhiman Hande, T. Polk, W. Walker, Dinesh Bhatia, “Indoor Solar Energy Harvesting for Sensor Network Router Nodes”, Journal of Microprocessors and Microsystems- Special Issue on Sensor Systems, Volume 31, Issue 6, pp. 381-392, September 2007.

Abhiman Hande, Todd Polk, William Walker, Dinesh Bhatia, “Self-Powered Wireless Sensor Networks for Remote Patient Monitoring in Hospitals” Sensors 2006, 6, 1102-1117, ISSN 1424-8220.

Parivallal Kannan and Dinesh Bhatia, “Interconnect Estimation for FPGAs”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 25, No. 8, pp 1523-1534, August 2006.

Shankar Balachandaran and Dinesh Bhatia, “A-priori Wirelength and Interconnect Estimation based on Circuit Characteristics”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 24. No 7 pp 1054-1065, July 2005

Manjunath Gangadhar and Dinesh Bhatia, “FPGA based EBCOT Architecture for JPEG 2000”, Journal of Microprocessors and Microsystems, Vol 29, 8-9, pp. 363-373, Nov 2005.

Shankar Balachandaran, Parivallal Kannan, and Dinesh Bhatia, “On Metrics for Routability Estimation for FPGAs”, IEEE Transactions on VLSI Systems, Vol. 12, No. 4, April 2004, pp. 381-385.

J. M. Emmert, S. Lodha, and Dinesh Bhatia, “On Using Tabu Search for Design Automation of VLSI Systems, Journal of Heuristics 9(1), pp. 75-90, January 2003, Kluwer Academic Publishers.

J. M. Emmert and Dinesh Bhatia, “Reconfiguring FPGA Mapped Design for Fault Tolerant Applications”, Journal of Electronic Testing, Volume 16, 591-606, 2000.

J.M. Emmert and Dinesh Bhatia, “Two-Dimensional Placement using TABU Search”, Journal of VLSI Design, Vol. 12, 13-23, 2001.
Dinesh Bhatia and James Haralambides, "Bounds, Designs, and Layouts for Multi-Terminal FPIC Architectures", INTEGRATION – The VLSI Journal, 28 (1999), 141-156.

Dinesh Bhatia and James Haralambides “Resource Requirements and Layouts for Field Programmable Interconnection Chips”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8. No 3., June 2000

Karthik Gajjalapurna and Dinesh Bhatia, “Temporal Partitioning and Scheduling Data Flow Graphs on Reconfigurable Computers”, IEEE Transactions on Computers, Vol. 48, No. 6, Pages 579-590. June 1999.

Dinesh Bhatia, “Field Programmable Gate Arrays”, Journal of VLSI Design, vol. 4, number 4, 1996.

Dinesh Bhatia and V. Shankar, “Greedy Segmented Channel Router”, Journal of VLSI Design, Vol. 5, No. 1, Pages 11-21, 1996.

Dinesh Bhatia and Amit Chowdhary “A Multi-Terminal Net Router for FPGAs”, Journal of VLSI Design, Vol. 4, No. 1, Pages 1-10, January 1996.

Dimitrios Kagaris, Spyros Tragoudas, and Dinesh Bhatia, “Pseudo-Exhaustive Built-In TPG for Sequential Circuits”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, Vol. 14, No. 9, Pages 1160-1171, September 1995.

R. P. Swaminathan, D. Giriaraj, and D. K. Bhatia. “The pagenumber of the class of bandwidth-k graphs is k – 1”, Information Processing Letters, 55(2):71-74, July 1995.

Giriraj Devaraj and Dinesh Bhatia, “Crosstalk Driven MCM Router”, Journal of Microelectronics Systems Integration, Pages 65–80, Vol. 2, No. 2, 1994.

 

Conference Publications

Sameer Arora, Poras T Balsara, Dinesh K Bhatia , IECON Paper

Girish Deshpande and Dinesh Bhatia, “Microchannels for Thermal Management in FPGAs”, International Conference on Reconfigurable Computing and FPGAs, December 4-6, 2017, Cancun, Mexico.

Athul A. Thulasi, Dinesh Bhatia, Poras T Balsara, Shalini Prasad, “Portable Impedance Measurement Device for Sweat based Glucose Detection” International Conference on Body Sensor Networks (BSN 2017), May 9-12, 2017, Eindhoven, The Netherlands.

Sameer Arora, Poras T Balsara, Dinesh K Bhatia, "Effect of sampling time and sampling instant on the frequency response of a boost converter", Industrial Electronics Society IECON 2016 - 42nd Annual Conference of the IEEE, pp. 7155-7160, 2016, “Best paper and Presentation Award”.
           
Sameer Arora, Poras T Balsara, Dinesh K Bhatia , “Digital Implementation of Constant Power Load (CPL), Active Resistive, Constant Current and Combinations” 2016 IEEE Dallas Circuits and Systems Conference (DCAS) , Arlington, TX, 2016, pp. 1-4.

Vishnoukumaar Sivaji, Dinesh Bhatia, Shalini Prasad, RF Powered Sleep Apnea Monitoring System, International Conference on Pervasive Technologies Related to Assistive Environments, Corfu, Greece, July 1-3 2015.


Vishnoukumaar Sivaji, Dinesh Bhatia, Shalini Prasad, “Novel Technique for Sleep Apnea Monitoring”, International Conference on Body Sensor Networks (BSN 2015), June 9-12, 2015, Boston, MA.


Sameer Arora, Poras T. Balsara, Dinesh Bhatia, Robert J. Taylor, Bob Hunt, “Gain and Phase (Gap) Measurement Device”, Applied Power Electronics Conference, March 15-19, 2015, Charlotte, NC.


Girish Deshpande and Dinesh Bhatia, Effect of Switchbox Topologies and Net Ordering on 3D FPGA Routing – a study, 10th IEEE Dallas Circuits and Systems Conference, October 2014.


Dinesh Bhatia and A. L. Praveen Aroul, “Building Reliable Wearable Body Sensor Communication”, International Conference on Pervasive Technologies Related to Assistive Environments, Rhodes Island, Greece, May 29-31 2013.


William Walker and Dinesh Bhatia, “Swallow Sounds for Automated Ingestion Detection”, IEEE-AMA Medical Technology Conference, Boston, October 2011.


William Walker and Dinesh Bhatia, “Swallow Sound Analysis for Automated Ingestion Detection”, ACM International Conference on Pervasive Technologies Related to Assistive Environments, Crete, Greece, July 2011, ISBN 978-1-4503-0772-7/11/05.


William Walker and Dinesh Bhatia, “Towards Automated Ingestion Detection: Swallow Sounds”, IEEE EMBC 2011, Boston, MA, pp. 7075-7078.


A. L. Praveen Aroul and Dinesh Bhatia, “Wire and Planar Antenna Performance Analysis and RF Propagation Characterization around Human Body”, Southern Biomedical Engineering Conference (SBEC 2011), April 29-May 1, 2011, Arlington, Texas.


Amit R. Shah, Antoine Lourdes Praveen Aroul, and Dinesh Bhatia, “HAMS: Health and Activity Monitoring System”, Eighth IASTED International Conference on Biomedical Engineering, February 16-18, 2011, Inssbruck, Austria.


Dinesh Bhatia, A.L. Praveen Aroul, William Walker, “A Pervasive Health Monitoring System for Connected Health”, First AMA-IEEE Medical Technology Conference on Individualized Healthcare, March 2010.


Arvind Rajasekaran, Abhiman Hande, Dinesh Bhatia, “Ultra-Low-Power Intelligent PWM Controller for Vibration Energy Harvesting Power Supplies”, IEEE Dallas Circuits and Systems Society (DCAS) Workshop, October 2009.


William Walker, A. L. Praveen Aroul, Dinesh Bhatia, “Mobile Health Monitoring System”, IEEE Engineering in Medicine and Biology Conference, Minneapolis, September 2009.


Achutan Manohar and Dinesh Bhatia, Pressure detection and wireless interface for patient bed” IEEE International Conference on Biomedical Circuits and Systems, Baltimore, pp. 389-392, October 2008.


Shilpa Bhoj and Dinesh Bhatia, “Early Stage FPGA Interconnect Leakage Power Estimation”, IEEE Intl. Conf. on Computer Design, Lake Tahoe, pp. 438-443, October 2008


Shilpa Bhoj and Dinesh Bhatia, “A Simulation Framework for dynamic thermal management in FPGAs”, IEEE Intl. Conf. on Field Programmable Logic and Applications, pp. 659-662, Heidelberg, Germany, August 2008


A.L. Praveen Aroul, Achutan Manohar, Dinesh Bhatia, Leonardo Estevez, “Power Efficient Multi-band Activity Monitoring for Assistive Environments”, Proceedings of ACM International Conference on Pervasive Technologies Related to Assistive Environments, Athens, July 2008, ISBN:978-1-60558-067-8


Arvindh Rajasekeran, Abhiman Hande, Dinesh Bhatia, “Buck-Boost Converter Based Power Conditioning Circuit for Low Excitation Vibrational Energy Harvesting”, 3rd Annual Austin Conference on Integrated Systems and Circuits, Austin, Texas, May, 2008.


Praveen Aroul, Dinesh Bhatia, Leonardo Estevez, “Energy Efficient Ambulatory Activity Monitoring for Disease Management”, IEEE Body Sensor Network Workshop, June 2008, Hong Kong.


Jay Shah, Praveen Aroul, Abhiman Hande, Dinesh Bhatia, “Remote Cardiac Activity Monitoring using Multihop Wireless Sensor Networks”, IEEE Engineering in Medicine and Biology Workshop, pp. 142-145, ISBN 978-1-4244-1626-4, November 2007.


Todd Polk, William Walker, Dinesh Bhatia, “A Wireless Telemedicine System with External Reporting Range and Priority Messaging”, IEEE Engineering in Medicine and Biology Workshop, pp. 138-145, ISBN 978-1-4244-1626-4, November 2007.


Dinesh Bhatia, Leonardo Estevez, and Shekar Rao, “Energy Efficient Contextual Sensing for Elderly Care”, IEEE Engineering and Medicine and Biology Conference, pp. 4052-4055, Lyon, France, August 2007.


Shilpa Bhoj and Dinesh Bhatia, “Pre-Route Interconnect Capacitance and Power Estimation in FPGAs”, IEEE International Conference on Field Programmable Logic and Applications, pp. 159-164, Amsterdam, Netherlands, August 2007.


Shilpa Bhoj and Dinesh Bhatia, “Thermal Modeling and Temperature Driven Placement for FPGAs” IEEE International Conference on Circuits and Systems (ISCAS), pp. 1053-1056, New Orleans, May 2007.


Narayan Subramanian, Rajarshee Bharadwaj, Dinesh Bhatia, “A Leakage Aware Design Methodology for Power-gated Programmable Architectures”, IEEE International Conference on Field Programmable Technology (FPT), pp. 301-304, Bangkok, Thailand, December 2006.


W. Walker, T. Polk, A. Hande, and D. Bhatia, “Remote Blood Pressure Monitoring Using a Wireless Sensor Network”, IEEE Sixth Annual Emerging Information Technology Conference, August 2006.


T. Polk, A. Hande, W. Walker, and D. Bhatia, “Wireless Telemetry for Oxygen Saturation Measurements”, IEEE Biomedical Circuits and Systems (BiOCAS) Conference, pp. 174-177, London, UK, November 2006


(**) Sanjay P. Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras Balsara, “Generic Network Interface for Plug and Play NoC based Architecture”, International Workshop on Applied Reconfigurable Computing (AR2006), Delft, The Netherlands, March 1-3, 2006. Lecture Notes in Computer Science, Volume 3985, pp. 287-298, 2006.


Rajan Konar, Rajarshee Bharadwaj, Dinesh Bhatia, Poras Balsara, “Exploring Logic Block Granularity in Leakage Tolerant Programmable Devices”, IEEE International Conference on VLSI Design, Hyderabad, pp. 754-757, 3-7 January 2006.

Rajarshee Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras Balsara, “FPGA Architecture for Standby Power Management”IEEE International Conference on Field Programmable Technology (FPT), Singapore, pp. 181-188, December 2005


S. Balachandaran, Dinesh Bhatia, “Timing Aware Interconnect Prediction Models for FPGAs”, International Conference on Field Programmable Logic (FPL 2005), Tampere, Finland, pp. 167-172, August 2005.

Mukesh Chugh, Dinesh Bhatia, Poras Balsara, “Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA”, 12th Reconfigurable Architectures Workshop RAW 2005. Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS ’05) Workshop 3 – Vol 4, p. 145.2, April 04 – 08, 2005.


R. Manimegalai, E. Siva Soumya, V. Muralidharan, B. Ravindran, V. Kamakoti, Dinesh Bhatia, “Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines”, 18th International Conference on VLSI Design, IEEE Press, January 2005. pp 451 - 456


Rajarshee Bhardwaj, Rajan Konar, Poras Balsara, Dinesh Bhatia, “Exploiting Temporal Idleness to Reduce Leakage in Programmable Architectures”,  10th Asia and South Pacific Design Automation Conference. Proceedings of the ASP-DAC 2005, Asia and South Pacific Vol 1, 18 – 21 Jan 2005, pp. 651 – 656, Vol 1.


Parivallal Kannan and Dinesh Bhatia, “Estimating Pre-Placement FPGA Interconnection Requirements”, Proceedings of the 17th International Conference on VLSI Design, IEEE Press, January 2004. pp 869-874, Jan 05 – 09, 2004.


Manjunath Gangadhar and Dinesh Bhatia, “FPGA Based EBCOT Architecture for JPEG 2000”, Proceedings of IEEE International Conference on Field Programmable Technology, Tokyo, 15 – 17 December 2003, pp 228 - 233.


Parivallal Kannan and Dinesh Bhatia, “Interconnect Estimation for FPGAs under Timing Driven Domains”, IEEE International Conference on Computer Design (ICCD), Proceedings of the 21st International Conference on Computer Design, p. 334, October 13 – 15 2003.


Parivallal Kannan and Dinesh Bhatia, “Interconnection Estimation for Segmented FPGA Architectures”, Proceedings of the 16th Annual IEEE International SoC Conference, September 2003, pp 295 – 296 , Sept 17 – 20, 2003 .


Shankar Balachandran and Dinesh Bhatia, “A-priori Wirelength and Interconnect Estimation Based on Circuit Characteristics”, ACM International Workshop on System Level Interconnect Prediction, Proceedings of the 2003 International Workshop on System Level Interconnect Prediction, pp 77-84, 2003.


(**) Parivallal Kannan, Shankar Balachandaran, Dinesh Bhatia, “Rapid and Reliable Routability Estimation for FPGAs”, International workshop on field programmable logic, Montpellier, France, September 2002. Lecture Notes in Computer Science,  Springer Verlag, Volume 2438, pp. 242-252.


Shankar Balachandaran, Parivallal Kannan, and Dinesh Bhatia, “On Metrics for Routability Estimation for FPGAs”, IEEE/ACM Design Automation Conference, New Orleans, Proceedings of the 39th Conference on Design Automation, pp. 70-75, June 10 – 14,  2002.


Shankar Balachandaran, Parivallal Kannan, and Dinesh Bhatia, “On Routing Demand and Congestion Estimation for FPGAs”, Proceedings of joint meeting of 7th Asia and South Pacific Design Automation Conference p.639 and 15th International Conference on VLSI Design, IEEE Press, 07 – 11 January 2002


(**) Parivallal Kannan and Dinesh Bhatia, “Tightly Integrated placement and routing for FPGAs”, International workshop on field programmable logic, August 2001. Lecture Notes in Computer Science, LNCS 21476, Springer Verlag, Volume 2147, pp. 233-242.


(**) Parivallal Kannan, Shankar Balachandaran, Dinesh Bhatia, “fGREP: Fast Generic Routing Demand Estimation for Placed FPGA Circuits International workshop on field programmable logic, August 2001. Lecture Notes in Computer Science, LNCS 2147, Springer Verlag, Volume 2147, pp. 233-242, ISBN 3-540-42499-7 (2001). Proceedings of the 11th International Conference on Field Programmable Logic & Applications, pp 233 – 242, Aug 27 – 29, 2001.


(**) J. M. Emmert and D. K. Bhatia, “Tabu Search: Ultra Fast FPGA Placement,” International workshop on field programmable logic, September 1999. Lecture Notes in Computer Science, Springer-Verlag, Volume 1673, pp. 81-90.


(**) Dinesh Bhatia, Kuldeep Simha, Parivallal Kannan, “NEBULA: A Partially and Dynamically Reconfigurable Computing Environment”, International workshop on field programmable logic, September 1999. Lecture Notes in Computer Science, Springer-Verlag, Volume 1673, pp. 81-90.


Ravi Kothari, Ming Dong, Dinesh Bhatia, "Neighborhood Induced Stochastic Resonance", International Joint Conference on Neural Networks, 1999. Vol 1, 10 -16 July 1999, pp 621 – 624 Vol 1.


J. M. Emmert and D. K. Bhatia, “A Methodology for Fast FPGA Floorplanning,” Proceedings of ACM Seventh International Symposium on Field-Programmable Gate Arrays, February 1999.


Gregory Tumbush and Dinesh Bhatia, " Clustering to Improve Bi-Partition Quality and Run Time", Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 30 May – 2 June 1999, pp 145 – 148 Vol 6, January 1999.


J. M. Emmert and D. K. Bhatia, “Incremental Routing in FPGAs,” Proceedings of 11th Annual IEEE International Application Specific Integrated Circuit Conference, pp 217 – 221, 13 - 16 September 1998.


Sandeep Lodha and Dinesh Bhatia, "Bi-partitioning using TABU Search", Proceedings of 11th Annual IEEE International Application Specific Integrated Circuit Conference, pp. 223 – 227, 13 – 16  September 1998.


(**) J. M. Emmert, A. Randhar, and D. K. Bhatia, “Fast Floorplanning for FPGAs,” International workshop on field programmable logic, September 1998. Lecture Notes in Computer Science, Springer-Verlag, Volume 1482, pp. 129-138, September 1998.


(**) Dinesh Bhatia, Karthik Gajjalapurna, Kuldeep Simha, Parivallal Kannan, “REACT: Reactive Environment for Runtime Reconfiguration”, International workshop on field programmable logic, September 1998. Lecture Notes in Computer Science, Springer-Verlag, Volume 1482, pp. 209-218, September 1998.


N. Venkateswaran and Dinesh Bhatia, "Clock-Skew Constrained Placement for Row Based Designs", Proceedings of International Conference on Computer Design (ICCD 98), pp. 219-220, Austin, October 1998.


Karthikeya M. Gajjala Purna and Dinesh Bhatia, "Partitioning in Time: A Paradigm for Reconfigurable Computing", Proceedings of International Conference on Computer Design (ICCD 98), pp. 340-347, Austin, October 1998.


Karthikeya M. Gajjala Purna and Dinesh Bhatia, "Emulating large designs on Small Reconfigurable Hardware", Proceedings of International Workshop on Rapid Systems Prototyping, Leuven, Belgium, June 3-5, 1998.


(**) J.M. Emmert and Dinesh Bhatia, “Partial Reconfiguration of FPGA Mapped Designs with Applications to Fault Tolerance and Yield Enhancement”, International Workshop on Field Programmable Logic, September 1997,  Lecture Notes in Computer Science, Springer Verlag, Volume 1304, pp. 141-150.


J. M. Emmert and D. K. Bhatia, “Reconfiguring FPGA Mapped Circuits,” CERC/VIUF/IEEE Computer Society Workshop on 21st Century Electronics Systems Design: Breakthroughs in Quality and Productivity, December 1997.


Arun Hegde and Dinesh Bhatia, "C to Synthesizable VHDL", CERC/VIUF/IEEE Computer Society Workshop on 21st Century Electronics Systems Design: Breakthroughs in Quality and Productivity, December 1997.


K.M. Gajjalapurna and Dinesh Bhatia, "Temporal Partitioning and Scheduling for Reconfigurable Computers", IEEE International Conference on FPGAs in Custom Computing Machines (FCCM 98), pp. 329-330, Napa Valley, April 1998.


Raghu Burra and Dinesh Bhatia, "Timing Driven Multi-FPGA Board Partitioning", Proceedings of IEEE International Conference on VLSI Design, Chennai, India, January 1998. Proceedings of the 11th International Conference on VLSI Design: VLSI for Signal Processing, p 234, Jan 04 – 07, 1998.


Gregory Tumbush and Dinesh Bhatia, “Partitioning under Area and Timing Constraints”, Proceedings IEEE International Conference on Computer Design (ICCD-97), pp. 614-620, Austin, September 1997.


Gregory Tumbush and Dinesh Bhatia, "K-way Partitioning under Timing, Pin, and Area Constraints", Proceeding of IEEE International Conference on Innovative Systems in Silicon (ISIS 97), pp. 95-106, Austin, October 1997.


Dinesh Bhatia, “Reconfigurable Computing” Proceedings of Tenth International Conference on VLSI Design, Hyderabad, India, January 04 - 17 1997, pp 356 - 359.


Jianzhong Shi and Dinesh Bhatia, “Performance Driven Floorplanning for Field-Programmable Gate Arrays”, ACM International Symposium on Field Programmable Gate Arrays, Monterey, pp. 112-118, February 1997.


V. Natesan, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri, “A Constructive Method for Data Path Area Estimation During High Level VLSI Synthesis”, Asia and South Pacific Design Automation Conference, (ASP-DAC), pp. 509-515, Chiba, Japan, January 1996.


Jianzhong Shi, Dinesh Bhatia, “Macro Block Floorplanning for FPGAs”, IEEE Tenth International Conference on VLSI Design, January 1997. IEEE Computer Society Press. Proceedings of the 10th International Conference on VLSI Design, pp 21 – 26, Jan 04 – 07, 1997.


Vijayananda Sankar, Dinesh Bhatia, “Multiway Partitioner for High Performance FPGA based Board Architectures”, IEEE International Conference on Computer Design (ICCD), Pages 579-585, Austin, October 1996.  IEEE Computer Society Press.


(**) Doug Smith, Dinesh Bhatia, “RACE: Reconfigurable and Adaptive Computing Environment”, International workshop on Field Programmable Logic (FPL), Darmstadt, Germany, September 1996. Lecture Notes in Computer Science, Vol. 1142, pp. 87-95.


Dinesh Bhatia, James Haralambides, “Bounds for Multi-Terminal Net Routings on FPICs”, Proceedings of Canadian workshop on Field-Programmable Logic, Pages 170-177, May 1996.


V. Natesan and Dinesh Bhatia, “Performance Driven Placement for Large Synthesized Designs”, Proceedings of 1995 IEEE ASIC Conference, Pages 237-240, Austin, September 1995. IEEE Computer Society Press.


Dinesh Bhatia, James Haralambides, “Resource Requirements for Field-Programmable Interconnection Chips”, Proceedings of Eighth International Conference on VLSI Design, Pages 376-380, New Delhi, India, January 1995. IEEE Computer Society Press.


Dinesh Bhatia, Vanitha Narasimhan, “Simple Yet Effective Replication for FPGA Partitioning”, Proceedings of IEEE Conference on Application Specific Integrated Circuits, ASIC-94, pp. 152-155, Rochester, September 1994. IEEE Computer Society Press.


Harold W. Carter, Dinesh Bhatia, “Automatic Test Vector Generation (ATPG) and Design for Testability for Field Programmable Gate Arrays: A University Perspective”, Invited paper, PLD Conference, San Jose, April 11–13, 1994.


V. Shankar, Dinesh Bhatia, “Generalized Routing for Row-Based FPGAs”, Proceedings of Fourth Great Lakes Symposium on VLSI, pp. 64-69, March 1994. IEEE Computer Society Press.


Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas, “Stochastic Model for Routability Analysis of FPGAs”, Proceedings of Fourth Great Lakes Symposium on VLSI, pp. 76-79, March 1994. IEEE Computer Society Press.


Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori, “Hierarchical Reconfiguration of VLSI/WSI Arrays”, Proceedings of VLSI-94, Calcutta, India, Pages 349-352, January 1994. IEEE Computer Society Press.


Amit Chowdhary, Dinesh Bhatia, “Detailed Routing of Multi-Terminal Nets in FPGAs”, Proceedings of VLSI-94, Calcutta, India, Pages 237-242, January 1994. IEEE Computer Society Press.


Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia, “Pseudoexhaustive BIST for Sequential Circuits”, Proceedings of International Conference on Computer Design, ICCD, Pages 523-526, October, 1993. IEEE Computer Society Press.


Dinesh Bhatia, “Post Simulation Hardware Prototyping”, Proceedings of 1993 SCS Western Multiconference, Pages 213-218, January 1993, San Diego, CA. Special session on Engineering Education.


(**) Dinesh Bhatia, Tom Leighton, Fillia Makedon, Carolyn Norton, “Improved Algorithms for Routing on Two-Dimensional Grids”, Proceedings of 18th Workshop on Graph Theoretic Concepts in Computer Science, Wiesbaden, Germany, pp. 114-122, June 1992. 


Dinesh Bhatia, “Routing with Short Wires and Small Channel Width”, Proceedings of 28th Allerton Conference on Communication, Control and Computing, Pages 112-121, Urbana-Champaign, Oct. 1990.


Dinesh Bhatia, “Restructuring Wafers for Maximum Yield and some Applications of WSI”, Proceedings of 2nd IEEE Symposium on Parallel and Distributed Computing, Pages 750-753, Dallas, Dec. 90. IEEE Computer Society Press.


J. David, Dinesh Bhatia, J. Haralambides, Fillia Makedon, “Rip Up and Reroute in a Global Routing Visualization System”, EURISCON ’91, The European Robotics and Intelligent Systems Conference, Corfu, Greece, June 91.


Dinesh Bhatia, Tom Leighton, Fillia Makedon, “Efficient Reconfiguration of WSI Arrays”, Proceedings of First International Conference on System Integration, pp. 46-57, Morristown, April 1990, IEEE Computer Society press.


Dinesh Bhatia, Fillia Makedon, “A Model for University Computer Learning Resource (CLEAR) Centers ” 2nd International Conference on Human-Computer Interaction”, Honolulu, Hawaii, August 1987.


John Gallant, Dinesh Bhatia, “Statistical Interface between Expert Systems and Databases”, New Directions in Database and Knowledge Management Systems, IEEE Computer Society Chapter, Dallas, March 10, 1987.

 

 

Erik Jonsson School of Engineering and Computer Science
University of Texas at Dallas