CS/CE 6397: Synthesis and Optimization of High-Performance Systems

Time: 1-2:15pm; Location: ECSS 2.306

(This page is under construction)
A comprehensive study of the high-level synthesis and optimization algorithms for designing high performance systems with multiple CPUs or functional units for critical applications such as Multimedia, Signal processing, Telecommunications, Network and Wireless applications, etc. Topics including algorithms for architecture-level synthesis, embedded software and systems, scheduling, real-time systems, highly parallel processor array design and mapping, optimal code generations for DSP processor, and hardware/software codesigns.

The department has offered very few courses about computer architectures and parallel systems. I hope that this course will fill some of the gaps. It will be very useful for your future career or advanced research because nowadays a system designer needs to understand software, OS, and architectures. I may not offer it again next time, so do not miss this chance.

My style of graduate teaching is to give students motivations and directions. I believe that a good graduate student should learn how to do research rather than spending all the time remembering materials or preparing for exams. There will be no in-class exams. A few homework will be given and term projects will be developed through a team work. Sometimes students will give presentations in class. I hope it is small class because I like to know each student personally in class. You will find that this course will be quite different from other grad. courses offered in UTD. And I am sure that you will enjoy it. Feel free to come to chat with me at anytime for anything. My office is at ES 3.226.

You do not need to worry about if you have enough pre-requisite knowledge or not. If you know the basic digital logic, and basic algorithms, you are more than enough. Don't worry. I am a good teacher. I will cover the required knowledge in class.




More detailed information can be found in The pdf version .

Some Possible Term Projects are listed here. Presentation dates: April 19 and 21, 2011. Presentation Order are listed here. Hard-copy and soft-copy report Due 1pm, April 26 (Tuesday).

Some Lecture Notes
  • Digitial Logic Review Slides ;
  • Logic Minimization Review Slides ;
  • Sorting + Introduction to Embedded Systems Slides ;
  • Adders and Multipliers Slides ;
  • Assignments and some handouts

    Reference Resources (UTD provides very good Electronic Database.)

    Some papers

    VHDL Resources (There are many. Search for yourself)

    Some DSP Related Links

    FPGA Links

    Other Intersting Links


    Revised by Edwin Sha - 2010.