Research Interests

Dr.Sha's research interests include Embedded Software, Information Security, DSP architectures and parallelizations, Embedded Systems, Compilers, Parallel architectures, High-level synthesis in VLSI, Software tools for parallel, distributed and embedded systems.

Resume in HTML version or postscript file or pdf file can be found here. The publication list should be complete in pdf version here.

The list of graduate students working with Dr. Sha (click here) .

His research summary and contribution can be found in HTML version or postscript file .

Research Projects

• Computer and Network Security.
• Optimizations for Embedded Systems and Software.
• Protecting Systems Against Buffer-Overflow Attacks via Hardware/Software.
• Very Fast Intrusion Detections.
• Loop Optimizations and Transformations for Parallel and Distributed Processing.
• Real-Time Fault Tolerance and Real-Time Communication on Parallel Architectures.
• Architectural Synthesis dealing with Imprecise Specifications.
• Optimal Data Scheduling and Partitioning for Parallel and Distributed Systems
• High-Level Synthesis and Code Generation for Multimedia Applications.

A Few Publications Listed here

Many recent papers can be found in my students web pages. Click here. The complete paper list can be found in Dr. Sha's resume.

Part of Journal Paper List

• ``Time-Constrained Loop Scheduling with Minimal Resources,"
  (with T. O'Neil ) Accepted in Journal of Embedded Computing (JEC) , June 2006.
  
  
• ``Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP,"
  (with M. Qiu, Z. Jia, C. Xue and Z. Shao ) Accepted in The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology , July 2006.
  
  
• ``Design Exploration with Imprecise Latency and Register Constraints,"
  (with C. Chantrapornchai and W. Surakumpolthorn) Accepted in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , March 2006.
  
  
• ``Energy Minimization for Heterogeneous Wireless Sensor Networks,"
  (with M. Qiu, C. Xue, Z. Shao and M. Liu) Accepted in Journal of Embedded Computing (JEC) , Sept. 2006.
  
  
• ``Loop Scheduling with Timing and Switching-Activity Minimization for VLIW DSP,"
  (with Z. Shao, C. Xue, Q. Zhuge and B. Xiao) in ACM Transactions on Design Automation of Electronic Systems, Vol. 11, No. 1, Jan. 2006, pp. 165 - 185.
  
  
• ``Optimizing Nested Loops with Iterational and Instructional Retiming,"
  (with C. Xue, Z. Shao, M. Liu and M. Qiu ) Accepted in Journal of Embedded Computing (JEC) , May 2006.
  
  
• ``Algorithms and Analysis of Scheduling for Loops with Minimum Switching,"
  (with Z. Shao, Q. Zhuge, M. Liu, C. Xue and B. Xiao) in International Journal of Computational Science and Engineering (IJCSE), Vol. 2, May 2006, pp. 88-97.
  
  
• ``The Fat-Stack and Universal Routing in Interconnection Networks,"
  (with K. Chen ) in Journal of Parallel and Distributed Computing, Vol. 66, No. 5, May 2006, pp. 705-715.
  
  
• ``Optimizing Address Assignment for Scheduling DSPs with Multiple Functional Units,"
  (with C. Xue, Z. Shao, Q. Zhuge, B. Xiao and M. Liu ) in IEEE Transactions on Circuits and Systems, Vol. 53, No. 9, September 2006, pp. 976 - 980.
  
  
• ``Hardware/software Optimization for Array & Pointer Bound Checking Against Buffer Overflow Attacks,"
  (with Z. Shao, J. Cao, K. Chan and C. Xue) in Journal of Parallel Distributed Computing, Vol. 66, No. 9, September 2006, pp. 1129 - 1136.
  
  
• ``Security Protection and Checking for Embedded System Integration Against Buffer Overflow Attacks via Hardware/Software,"
  (with Z. Shao, C. Xue, Q. Zhuge, M. Qiu and B. Xiao ) in IEEE Transactions on Computers, Vol. 55, No. 4, April 2006, pp. 443 - 453.
  
  
• ``Design Optimization and Space Minimization Considering Timing and Code Size via Retiming and Unfolding,"
  (with Q. Zhuge, C. Xue, Z. Shao, M. Liu and M. Qiu ) in Journal of Microprocessors and Microsystems, Vol. 30, Issue 4, June 2006, pp. 173-183.
  
  
• ``Efficient Assignment and Scheduling for Heterogeneous DSP Systems,"
  (with Z. Shao, Q. Zhuge and c. Xue) in IEEE Transaction on Parallel and Distributed Systems, Vol. 16, No. 6, June 2005, pp. 516-525.
  
  
• ``A Novel Multiplexer-Based Low-Power Full Adder,"
  (with Y. Jiang, A. Al-Sheraidah, Y. Wang and J. Chung) in IEEE Transactions on Circuits and Systems II, Vol. 51, No. 7, July 2004, pp. 345-348.
  
  
• ``Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation,"
  (with T. W. O'Neil) in Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 39, March 2005, pp. 273-293.
  
  
• ``Algorithms and Analysis of Scheduling for Loops with Minimum Switching,"
  (with Z. Shao, Q. Zhuge, M. Liu, C. Xue and B. Xiao) in International Journal of Computational Science and Engineering (IJCSE), , Vol. 2, 2004, pp. 11-18.
  
  
• ``Code Size Reduction Technique and Implementation for Software-Pipelined DSP Applications,"
  (with Q. Zhuge and B. Xiao) in ACM Transactions on Embedded Computing Systems (TECS), Vol. 2, No. 4, Nov. 2003, pp. 590-613.
  
  
• ``Algorithms and Analysis of Scheduling for Low-Power High-Performance DSP on VLIW Processors,"
  (with Z. Shao, Q. Zhuge and Y. Zhang ) in International Journal of High Performance Computing and Networking (IJHCN), Vol. 1, 2004, pp. 3-16.
  
  
• ``Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking,"
  (with B. Xiao and Q. Zhuge) in International Journal of Computers and Their Applications, Vol. 11, No. 1, March 2004, pp. 60-75.
  
  
• ``Communication Scheduling with Re-routing based on Static and Hybrid Techniques,"
  (with D. Surma and N. Passos) in Journal of Circuits, Systems and Computers, Vol. 13, No. 5, Oct. 2004, pp. 1039-1064.
  
  
• ``Efficient Variable Partitioning and Scheduling for DSP Processors with Multiple Memory Modules,"
  (with Q. Zhuge, B. Xiao and C. Chantrapornchai) in IEEE Transactions on Signal Processing, Vol. 52, No. 4, April 2004, pp. 1090-1099.
  
  
• ``Efficient Polynomial-time Nested Loop Fusion with Full Parallelism,"
  (with T. W. O'Neil and N. Passos) in International Journal of Computers and Their Applications, Vol. 10, No. 1, March 2003, pp 9-24.
  
  
• ``Partitioning and Scheduling DSP Applications with Maximal Memory Acess Hiding."
  (with Z. Wang) in Eurasip Journal on Applied Singal Processing, Number 9, September 2002, pp. 926-935.
  
  
• ``Efficient Module Selection for Finding Highly Acceptable Designs Based on Inclusion Scheduling."
  (with C. Chantrapornchai and S. X. Hu) in Journal of Systems Achitecture, Vol. 46, Number 11, 2000, pp. 1047-1071.
  
  
• ``Estimating Probabilistic Timing Performance for Real-time Embedded Systems."
  (with X. Hu and T. Zhou) in IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 9, Number 6, Dec. 2001, pp. 833-844.
  
  
• ``Retiming Synchronous Data-Flow Graphs to Minimize Execution Time."
  (with T. Q. O'Neil) in IEEE Transactions on Signal Processing, Vol. 49, Number 10, October 2001, pp. 2397-2407.
  
  
• ``Optimal Loop Scheduling for Hiding Memory Latency Based on Two Level Partitioning and Prefetching, "
  (with Z. Wang and T. Q. O'Neil) in IEEE Transactions on Signal Processing
  
  
• ``Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching,"
  (with Z. Wang and T. W. O'Neil) in Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology , Vol. 27, Jan. 2001, pp. 215-233.
  
  
• ``Communication Reduction in Multiple Multicasts based on Hybrid Static-Dynamic Scheduling,"
  (with D. R. Surma) in IEEE Transactions on Parallel and Distributed Systems.
  
  
• ``Optimizing Overall Loop Schedules using Prefetching and Partitioning,''
  (with F. Chen, and T. W. O'Neil) in IEEE Transactions on Parallel and Distributed Systems. Vol. 11, No. 6, June 2000, pp. 604-614.
  
  
• ``Efficient Acceptable Design Exploration Based on Module Utility Selection,"
  (with C. Chantrapornchai, and X. Sharon Hu) in
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. 1, Jan. 2000, pp. 19-29.
  
  
• ``Probabilistic Loop Scheduling for Applications with Uncertain Execution Time,"
  (with S. Tongsima, C. Chantrapornchai, D. Surma and N. Passos) in
  IEEE Transactions on Computers, Vol. 49, No. 1, Jan. 2000, pp. 65-80.
  
  
• ``Properties and Algorithms for Unfolding of Probabilistic Data-flow Graphs,"
  (with S. Tongsima, T. W. O'Neil, and C. Chantrapornchai) Accepted for publication in
  Journal of VLSI Signal Processing.
  
  
• ``Efficient Module Selections for Finding Highly Acceptable Designs based on Inclusion Scheduling,''
  (with C. Chantrapornchai, and X. S. Hu) Accepted for publication in
  Journal of Systems Architecture.
  
  
• ``Optimizing Page Replacement for Multiple-Level Memory Hierarchy,"
  (with C. Chantrapornchai) in
  International Journal of Computers and Their Applications Vol. 6, No. 4, Dec. 1999, pp. 212-222.
  
  
• ``Scheduling of Uniform Multi-Dimensional Systems under Resource Constraints," (with N. Passos) in
  IEEE Transactions on VLSI Systems, Vol. 6, No. 4, December 1998, pp. 719-730.
  
  
• ``Collision Graph based Communication Scheduling for Parallel Systems,"
  (with D. R. Surma) in
  International Journal of Computers and Their Applications. Vol. 5, No. 1, March 1998.
  
  
• ``Rotation Scheduling: A Loop Pipelining Algorithm,"
  (with L.-F. Chao and A. LaPaugh) in
  IEEE Transactions on Computer Aided Design , Vol. 16, No. 3, March 1997, pp. 229-239.
  
  
• ``Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops,"
  (with S. Tongsima, C. Chantrapornchai, and N. Passos) in
  IASTED International Journal of Parallel and Distributed Systems and Networks, Vol. 1, No 4, 1998, pp. 204-211.
  
  
• ``Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling,"
  (with S. Tongsima, C. Chantrapornchai and N. Passos) in
  Journal of VLSI Signal Processing, Vol. 18, 1998, pp. 111-123.
  
  
• ``Communication Sensitive Loop Scheduling for DSP Applications,"
  (with S. Tongsima and N. Passos), (regular paper),
  IEEE Transactions on Signal Processing Vol. 45, No. 5, May 1997, pp. 1309-1322.
  
  
• ``Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization,"
  (with N. Passos and L.-F. Chao), (regular paper),
  { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, Vol. 16, No. 2, February 1997, pp. 146-159.
  
  
• ``Minimization of Memory Access Overhead for Multi-dimensional DSP Applications via Multi-level Partitioning and Scheduling,"
  (with Q. Wang and N. Passos), Accepted for publication (regular paper),
  IEEE Transactions on Circuits and Systems II. Vol. 44, No. 9, September 1997, pp. 741-753.
  
  
• ``Hardware/Software Co-design With the HMS Framework,"
  (with M. Sheliga) (regular paper), in
  Journal of VLSI Signal Processing Systems, Vol. 13, No. 1, August 1996, pp. 37-56.
  
  
• ``Achieving Full Parallelism using Multi-Dimensional Retiming,"
  (with N. Passos) (regular paper),
  IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 11, November 1996, pp. 1150-1163.
  
  
• ``Synchronous Circuit Optimization via Multi-Dimensional Retiming," (Part 1)
  (Part 2) (with N. Passos), (regular paper), in
  IEEE Transactions on Circuits and Systems, vol II - Analog and Signal Processing, Vol. 43, No. 7, July 1996, pp. 507-519.
  
  
• ``Optimizing DSP Flow Graphs via Schedule-Based Multi-Dimensional Retiming,"
  (with N. Passos and S. C. Bass),
  IEEE Transactions on Signal Processing}, Vol. 44, No. 1, January, 1996, pp. 150-156.
  
  
• ``Optimal Data Scheduling for Uniform Multi-dimensional Applications,"
  (with Q. Wang, and N. Passos)
  IEEE Transactions on Computers, Vol. 45, No. 12, December 1996, pp. 1439-1444.
  
  
• ``Static Scheduling for Synthesis of DSP Algorithms on Various Models," < br> (with L.-F. Chao), (regular paper)
  Journal of VLSI Signal Processing, Vol 10, pp 207-223, 1995.
  
  
• ``Scheduling Data-Flow Graphs via Retiming and Unfolding,"
  (with L.F. Chao) in (regular paper)
  IEEE Transactions on Parallel and Distributed Systems Vol. 8, No. 12, December 1997, pp. 1259-1267.
  
  
• ``Maintaining Bipartite Matchings in the Presence of Failures,''
  (with K. Steiglitz), (regular paper)
  Networks} Journal, Vol. 23, no. 5, Aug. 1993, pp. 459-471.
  
  
• ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,''
  (with K. Steiglitz), (regular paper)
  IEEE Transactions on Computers, vol. 42, no. 7, July, 1993, pp. 854-862.
  
  
• ``Error Detection in Arrays via Dependency Graphs,''
  (with K. Steiglitz), (regular paper)
  Journal of VLSI Signal Processing, vol. 4, no. 4, October 1992, pp 331-342.
  
  
• "Rapid Prototyping Implementation and Optimization based on Conceptual Specification for Fuzzy Applications," (with C. Chantrapornchai, M. Sheliga and S. Tongsima) submitted to to Journal of Fuzzy Sets and Systems.
  
  
• Z. Wang an E. H.-M. Sha, ``Multiple Loop Nests Scheduling by Integrating Loop Partitioning and Data Padding" submitted to ACM Transcations in Embedded Computing Systems.
  
  
• T. W. O'Neil and E. H.-M. Sha, ``Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation," submitted to IEEE Transcations on Circuits and Systems II: Analog and Digital Signal Processing.
  
  
• T. W. O'Neil and E. H.-M. Sha, ``Time-Constrained Loop Scheduling with Minimal Resources," submitted to IEEE Transactions on Signal Processing.
  
  
• Q. Zhuge, Z. Shao, B. Xiao,and E. H.-M. Sha, ``Design Space Minimization with Timing and Code Size Optimization for DSP Applications," submitted.
  
  
• Q. Zhuge, Z. Shao, and E. H.-M. Sha, ``Optimization of Nest-Loop Software Pipelining," submitted.
  
  

Referred Conference Papers

• M. Qiu, Z. Jia, Z. Shao, C. Xue, Y. Liu and E. H.-M. Sha, ``Loop Scheduling to Minimize Cost with Data Mining and Prefetching for Heterogeneous DSP,"
  in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Dallas, Texas, Nov. 2006.
  
  
• K. Chen, S.Q. Zheng, E. H.-M. Sha, ``QoS Guarantee in Input-Queued Switches with Noniterative Schedulers,"
  in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Dallas, Texas, Nov. 2006.
  
  
• M. Liu, C. Xue, M. Qiu and E. H.-M. Sha, ``Optimizing Timing and Code Size Using Maximum Direct Loop Fusion,"
  in Proc. The 19th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2006), San Francisco, CA, Sept. 2006.
  
  
• M. Qiu, C. Xue, Q. Zhuge, Z. Shao, M. Liu and E. H.-M. Sha, ``Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability,"
  in Proc. IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Steamboat Springs, Colorado, Sept. 2006.
  
  
• M. Qiu, C. Xue, Z. Shao, Q. Zhuge, M. Liu and E. H.-M. Sha, ``Efficient Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network,"
  in Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), Seoul, Korea, August, 2006.
  
  
• C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, ``Loop Striping: Maximizing Parallelism for Nested Loops,"
  in Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), Seoul, Korea, August, 2006.
  
  
• M. Sheliga, E. H.-M. Sha and N. Passos, ``Reducing Inter Iteration Dependency Delays in Multiprocessor Systems for Large Graphs,"
  in Proc. The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2006), Orlando, Florida, USA, July 2006, 6 pages, CD Proceedings, Received the Best Paper Award.
  
  
• M. Qiu, Z. Shao, Q. Zhuge, C. Xue, M. Liu and E. H.-M. Sha, ``Efficient Assignment with Guaranteed Probability for Heterogeneous Parallel DSP,"
  in Proc. The 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2006), Minneapolis, MN, July 2006, pp. 623 - 630.
  
  
• C. Xue, Z. Shao, M. Liu, M. Qiu, E. H.-M. Sha, ``Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture,"
  in Proc. The 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2006), Minneapolis, MN, July 2006, pp. 375-382.
  
  
• K. Chen, E. H.-M. Sha and S. Q. Zheng, ``A Fast Non Iterative Scheduler for Input-Queued Switches with Unbuffered Crossbars,"
  in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005, pp. 126-131.
  
  
• M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, ``Maximum Loop Distribution and Fusion for Two-Level Loops Considering Code Size,"
  in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005, pp. 126-131.
  
  
• M. Qiu, M. Liu, C. Xue, Z. Shao, Q. Zhuge and E. H.-M. Sha, ``Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems,"
  in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005, pp. 295-300.
  
  
• T. W. O'Neil and E. H.-M. Sha, ``Static Scheduling of Split-Node Data Flow Graphs,"
  Accepted in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005, pp. 125-130.
  
  
• M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, ``Loop Distribution and Fusion Considering Timing and Code Size for Embedded DSP,"
  Accepted in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05), Nagasaki, Japan, Dec. 2005, pp. 121-130.
  
  
• C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, ``Optimizing Nested Loops with Iterational and Instructional Retiming,"
  Accepted in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05), Nagasaki, Japan, Dec. 2005, pp. 164-173.
  
  
• C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, ``Iterational Retiming: Maximize Iteration-Level Parallelism for Nested Loops,"
  Accepted in Proc. The 2005 ACM/IEEE/IFIP International Conference on Hardware - Software Codesign and System Synthesis (ISSS-CODES'05), New York, New York, Sept. 2005.
  
  
• K. Chen, M. Liiu, E. H.-M. Sha, ``A Feasible Baseline Architecture for Building and Evaluating Distributed Systems,"
  Accepted in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, Japan, Sept. 2005.
  
  
• M. Liu, Z. Shao, C. Xue, K. Chen, E. H.-M. Sha, ``Multi-level Loop Fusion with Minimal Code Size,"
  Accepted in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, Japan, Sept. 2005.
  
  
• B. Xiao, W. Chen, Y He and E. H.-M. Sha, ``An Active Detecting Method Against SYN Flooding Attack,"
  in Proc. The 11th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2005), Volume I, pp 709-715, Fukuoka, Japan, July 2005.
  
  
• Y. Chen, Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems,"
  in Proc. the 11th International Conference on Parallel and Distributed Systems (ICPADS'05), Volume II, The IEEE/IFIP International Workshop on Parallel and Distributed EMbedded Systems (PDES 2005), pp 2-6, Fukuoka, Japan, 20-22 July 2005 (Best workshop paper).
  
  
• K. Chen, B. Xiao and E. H.-M. Sha, ``Universal Routing in Distributed Networks,"
  in Proc. the 11th International Conference on Parallel and Distributed Systems (ICPADS'05), Volume II, The First International Workshop on Distributed, Parallel and Network Applications (DPNA-2005), pp 555-559, Fukuoka, Japan, 20-22 July 2005.
  
  
• Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, ``Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software"
  in Proc. IEEE International Conference on Information Technology (ITCC 05), Las Vegas, NV, April 2005, pp. 780-785.
  
  
• C. Xue, Z. Shao, Y. Chen and E. H.-M. Sha, ``Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation,"
  in Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, Philadelphia, PA, March 2005, Vol. 5, pp. 85-88. (Winner of the Best Student Paper).
  
  
• Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``High-level Synthesis for DSP Applications using Heterogeneous Functional Units,"
  in Proc. IEEE Asia and South Pacific Design Automation Conference (ASP DAC 05), Shanghai, China, Jan. 2005, pp. 302-304.
  
  
• T. O'Neil and E. H.-M. Sha, ``Using Unfolding to Minimize Inter-Iteration Dependencies",
  in Proc. IASTED 16th Int. Conf. Parallel and Distributed Computing and Systems (PDCS 04), Cambridge MA, November 2004, pp. 342-347. (Nominee for best paper.)
  
  
• Z. Shao, Q. Zhuge, B. Xiao and E. H.-M. Sha, `` Switching-Activity Minimization on Instruction-level Loop Scheduling for VLIW DSP Applications,"
  in Proc. IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 04), Galveston, Texas, September, 2004, pp. 224-234.
  
  
• M. Liu, Q. Zhuge, Z. Shao and E. H.-M. Sha, `` General Loop Fusion Technique for Nested Loops Considering Timing and Code Size,"
  in Proc. ACM/IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Washington DC, September 2004, pp. 190-201.
  
  
• B. Xiao, J. Cao, Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Dynamic Shortest Path Tree Update for Multiple Link State Decrements,"
  in Proc. IEEE Global Telecommunications Conference (Globecom), Dallas, Texas, November, 2004.
  
  
• M. Liu, Q. Zhuge, Z.. Shao, K. Chen and E. H.-M. Sha, ``Loop Fusion via Retiming for DSP Applications,"
  in Proc. 17th International Conference on Parallel and Distributed Computing Systems (PDCS), San Francisco , California, September, 2004, pp. 403 - 408.
  
  
• K. Chen and E. H.-M. Sha, ``The Fat-Stack and Universal Routing in Interconnection Networks,"
  in Proc. 17th International Conference on Parallel and Distributed Computing Systems (PDCS), San Francisco , California, September, 2004, pp. 321 - 326.
  
  
• Q. Zhuge, Z. Shao, and E. H.-M. Sha, ``Timing Optimization of Nested Loops Considering Code Size for DSP Applications,"
  in Proc. International Conference on Parallel Processing (ICPP), Montreal, Canada, August, 2004, pp. 475-482.
  
  
• C. Chantrapornchai, W. Surakumpolthorn, and E. H.-M. Sha, ``Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints,"
  in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC), Lecture Note in Computer Science, Springer, Aizu-Wakamatsu City, Japan, August, 2004, pp. 259-270.
  
  
• X. Chun, Z. Shao, E. H.-M. Sha and B. Xiao, ``Optimizing Address Assignment for Scheduling Embedded DSPs,"
  in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC), Lecture Note in Computer Science, Springer, Aizu-Wakamatsu City, Japan, August, 2004, pp. 64-73.
  
  
• Z. Shao, Q. Zhuge, M. Liu, E. H.-M. Sha and B. Xiao, ``Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-functional-unit Architectures,"
  in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC), Lecture Note in Computer Science, Springer, Aizu-Wakamatsu City, Japan, August, 2004, pp. 53 - 63.
  
  
• B. Xiao, J. Cao and E. H.-M. Sha, ``Maintaining Comprehensive Resource Availability in P2P Networks,"
  in Proc. IEEE The Third International Conference on Grid and Cooperative Computing (GCC 2004), Wuhan, China, October, 2004.
  
  
• B. Xiao, J. Cao, Q. Zhuge, Z. Shao, and E. H.-M. Sha, ``Dynamic Update of SPT in OSPF,"
  in Proc. 2004 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2004), Hong Kong, May, 2004, pp. 18-23.
  
  
• B. Xiao, J. Cao, Q. Zhuge, Y. He and E. H.-M. Sha, ``Approximation Algorithms Design for Disk Partial Covering Problem,"
  in Proc. 2004 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2004), Hong Kong, May, 2004, pp. 104-109.
  
  
• Z. Shao, Q. Zhuge, Y. He, C. Xue, M. Liu, and E. H.-M. Sha, ``Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units,"
  in Proc. IEEE International Parallel and Distributed Processing Symposium (IPDPS), (Regular paper) Santa Fe, New Mexico, April, 2004, pp. 891-900.
  
  
• Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, ``Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks,"
  in Proc. IEEE International Conference on Information Technology, (ITCC) , Information Assurance and Security Track, Las Vegas, Nevada, April, 2004, Vol. 1, pp. 409-413.
  
  
• Z. Shao, Q. Zhuge, Y. He and E. H.-M. Sha, ``Defending Embedded Systems Against Buffer Overflow via Hardware/Software,"
  Accepted in IEEE 19th Annual Computer Security Applications Conference, Las Vegas, Dec. 2003.
  
  
• Y. He, Z. Shao, B. Xiao, Q. Zhuge and E. Sha, ``Reliability Driven Task Scheduling for Tightly Coupled Heterogeneous Systems,"
  in IASTED International Conference on Parallel and Distributed Computing and Systems, Marina Del Ray, CA, Nov. 2003.
  
  
• B. Xiao, Q. Zhuge, Y. He, Z. Shao and E. Sha, ``Algorithms for Disk Covering Problems with the Most Points,"
  in IASTED International Conference on Parallel and Distributed Computing and Systems, Marina Del Ray, CA, Nov. 2003.
  
  
• Q. Zhuge, Z. Shao, B. Xiao and E. H.-M. Sha, ``Design Space Minimization with Timing and Code Size Optimization for Embedded DSP,"
  in Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2003), Newport Beach, California, Oct. 2003, pp. 144-149. (Nominated for the best paper as one of the final four).
  
  
• Z. Shao, Q. Zhuge, Y. Zhang and E. H.-M. Sha, ``Efficient Scheduling for Low-Power High-Performance DSP Applications,"
  in The 2nd Workshop on Hardware/Software Support for High Performance Scientific and Engineering Computing in conjunction with The 12th International Conference on Parallel Architecture and Compilation Techniques (PACT 2003), New Orleans, Louisiana, Sept. 2003.
  
  
• B. Xiao, Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Design and analysis of improved shortest path tree update for network routing,"
  in Proc. ISCA 16th International Conference on Parallel and Distributed Computing Systems, Reno, Nevada, August 2003, pp. 82-87.
  
  
• Q. Xu, E. H.-M. Sha and Y. Zhang, ``Application-Specific Interconnection Network design in Clustered DSP Processors,"
  in Proc. ISCA 16th International Conference on Parallel and Distributed Computing Systems, Reno, Nevada, August 2003, pp. 69-75.
  
  
• Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``An Integrated Framework of Design Optimization and Space Minimization for DSP Applications,"
  in Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 2003, vol. V, pp. 601-604.
  
  
• Z. Shao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Loop Scheduling for Minimizing Schedule Length and Switching Activities,"
  in Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 2003, vol. V, pp. 109-112.
  
  
• Z. Wang, S. Hu and E. H.-M. Sha, ``Register Aware Scheduling for Distributed Cache Clustered Architecture,"
  in Proc. IEEE/ACM 2003 ASP Design Automation Conference, Kitakyusyu, Japan, Jan. 2003.
  
  
• B. Xiao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Analysis and algorithms for partitioning of Large-Scale Adaptive Mobile Networks,"
  in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, Nov. 2002, pp. 308-313.
  
  

• T. O'Neil and E. H.-M. Sha, ``Unfolding a Split-Node Data-Flow Graph,"
  in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, Nov. 2002, pp. 717-722.
  
  

• Q. Zhuge, E. H. -M. Sha, C. Chantrapornchai, ``CRED: Code Size Reduction Technique and Implementation for Software-Pipelined Applications,"
  in Proc. IEEE Workshop On Embedded System Codesign (ESCODES'02)n conjunction with The 8th IEEE Real-Time and Embedded Technology and Applications Symposium, San Jose, CA, Sept. 2002,pp. 50-56.
  
  

• Q. Zhuge, B. Xiao, Z. Shao, E. H.-M. Sha and C. Chantrapornchai, ``Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops,"
  in Proc. ACM International Symposium on System Synthesis (ISSS), Kyoto, Japan, Nov. 2002, pp. 144-149.
  
  

• B. Xiao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Enhanced Route Maintenance for Dynamic Source Routing in Mobile Ad Hoc Networks,"
  in Proc. ISCA 15th International Conference on Parallel and Distributed Computing Systems (PDCS), Louisville, Kentucky, Sept. 2002, pp. 72-77.
  
  

• T. O'Neil and E. H.-M. Sha, ``Using Retiming to Minimize Inter-Iteration Dependencies,"
  in Proc. ISCA 15th International Conference on Parallel and Distributed Computing Systems (PDCS), Louisville, Kentucky, Sept. 2002, pp. 482-487.
  
  

• Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications,"
  in Proc. International Conference on Parallel Processing, Vancouver, Canada, August 2002, pp. 613-620.
  
  

• Z. Shao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Analysis And Algorithms For Scheduling With Minimal Switching Activities,"
  in Proc. IEEE Midwest Symposium on Circuits and Systems, Tulsa Oklahoma, August 2002, I372-I375, CD Proceedings.
  
  

• Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Performance Optimization of Multiple Memory Architectures for DSP"
  in Proc. IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 2002, pp. 469-472.
  
  

• T. W. O'Neil and E. H.-M. Sha, ``Minimizing Resources in a Repeating Schedule for a Split-Node Data-Flow Graph,"
  in Proc. ACM 12th Great Lakes Symposium on VLSI, New York, New York, April 2002, pp. 136-141.
  
  

• Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP ,"
  in Porc. Workshop on Parallel and Distributed Computing in Image Processing, Video Processing, and Multimedia (PDIVM'2002) in conjunction with IEEE International Parallel and Distributed Processing Symposium (IPDPS 2002), Fort Lauderdale, Florida, April 2002.
  
  

• Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Exploring Variable Partitioning for Dual Data-Memory Bank Processors,"
  in Proc. Third Workshop on Media and Streaming Processors in conjuction with IEEE/ACM 34th International Symposium on Microarchitecture, Austin, Texas, Dec. 2001, pp 45-52.
  
  

• B. Xiao, Q. Zhuge, and E. H.-M. Sha, ``Minimum Dynamic Update for Shortest Path Tree Construction,"
  in Proc. IEEE 2001 GLOBECOM, San Antonio, Texas, Nov. 2001, Vol. 1, pp. 126-131.
  
  

• Z. Wang, E. H.-M. Sha and X. Hu, ``Combining Partitioning and Data Padding for Scheduling Multiple Loop Nests," in Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Atlanta, GA, Nov. 2001, pp. 67-75.
  
  

• Z. Wang, Q. Zhuge and E. H.-M. Sha, ``Scheduling and Partitioning for Multiple Loop Nests,"
  in Proc. 14th ACM/IEEE Internatioanl Symposium on System Synthesis (ISSS), Montréal, Québec, Canada, October, 2001, pp. 183-188.
  
  

• Y. Jiang, Y. Wang and E. H.-M. Sha, ``On Low-Power Array Multipliers," in Proc. 8th International IEEE Conference on Electronics, Circuits, and Systems (ICECS 2001), Malta, Sept. 2001.
  
  

• Y. Jiang, Y. Wang and E. H.-M. Sha, ``Comprehensive Power Evaluation of CMOS Full Adders," in 9th Int. Symposium on Integrated Circuits, Devices & Systems (ISIC 2001), Singapore, Sept. 2001.
  
  

• T. O'Neil and E. H.-M. Sha, ``On Retiming Synchronous Data-Flow Graphs,"
  in ISCA 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August, 2001, pp. 103-108.
  
  

• B. Xiao, Q. Zhuge and E. H.-M. Sha, ``Efficient Update of Shortest Path Routing Algorithms for Network Routing,"
  in ISCA 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August, 2001, pp. 315-320.
  
  

• Y. Jiang, Y. Wang and E. H.-M. Sha, ``Distributed Scaling Algorithm for FFT Computation Using Fixed Point Arithmetic," in ISCA 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August, 2001, pp. 490-495.
  
  

• Y. Jiang, A. Al-Sheaidah, Y. Wang, and E. H.-M. Sha, ``A Set of Novel Multiplexer-based Architectures for Full Adder," in Proc. IEEE/WSES World Multiconference on Circuits, Systems, Communications and Computers, Crete, Greece, July, 2001.
  
  

• J. Xu, E. H.-M. Sha, ``Implementing Parallelism and Scheduling Data Flow Graphs on Java Virtual Machine,"
  in Proc. IEEE International Conference On Acoustics, Speech, and Signal Processing, Salt Lake City, Utah, May, 2001.
  
  

• Z. Wang, E. H.-M. Sha and Y. Wang, ``Optimal Partitioning and Balanced Scheduling with the Maximal Overlap of Data Footprints,"
  in Proc. IEEE/ACM 11th Great Lakes Symposium on VLSI, West Lafayette, Indiana, March 2001.
  
  

• V. Andronache, E. H.-M. Sha, and N. Passos, ``Design and Analysis of Efficient Application-Specific On-Line Page Replacement Techniques for Distributed Memory Systems," in Proc. 12th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, November, 2000, pp. 551-556.
  
  

• T, O'Neil and E. H.-M. Sha, ``Optimal Graph Transformation using Extended Retiming with Minimal Unfolding,"
  in Proc. 12th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, November, 2000, pp. 128-133.
  
  

• T, O'Neil, E. H.-M. Sha and S. Tongsima, ``Parallelizing Synchronous Data-Flow Graphs via Retiming,"
  in Proc. the 4th International Conference on Algorithms and Architectures for Parallel Processing, Hong Kong, December, 2000, pp. 252-263.
  
  

• R. Light, W. Maxfield, B. Reed, N. L. Passos, and E. H.-M. Sha, ``Improving Nested Loops' ILP on a Parallel ASIC Design," in ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August, 2000, pp. 105-110.
  
  

• T. O'Neil and E. H.-M. Sha, ``Minimizing Inter-Iteration Dependencies for Loop Pipelining,"
  in ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August, 2000, pp. 412-417.
  
  
• Z. Wang, M. Kirkpatrick, and E. H.-M. Sha, ``Optimal Two Level Partitioning and Loop Scheduling for Hiding Memory Latency for DSP Applications,"
  in Proc. ACM 37th Design Automation Conference , Los Angeles, California, June, 2000
  
  
• J. Ding, J. C. Furgeson and Edwin H..-M. Sha, "Application Specific Image Compression for Virtual Conferencing,"
  in Proc. IEEE International Conference on Information Technology: Coding and Computing, Las Vegas, Nevada, March 2000.
  
  
• J. Ding, M. Kirkpatrick, and E. H.-M. Sha, ``QoS Measures and Implementations Based on Various Models for Real-time Communications,"
  in Proc. 3rd IEEE Symposium on Application-Specific Systems and Software Engineering Technology, Richardson, Texas, March, 2000.
  
  
• C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Algorithms for Acceptable Design Exploration," in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000.
  
  
• V. Andronache, E. H.-M. Sha and N. Passos, ``Design and Analysis of Efficient Application-Specific On-line Page Replacement Techniques,"
  in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000.
  
  
• T. W. O'Neil, and Edwin H.-M. Sha, ``Rate-Optimal Graph Transformation Based on Extended Retiming and Unfolding,"
  in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999.
  
  
• Z. Wang, V. Andronache, and Edwin H.-M. Sha , ``Optimal Partitioning under Memory Constraints for Minimizing Average Schedule Length,"
  in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999.
  
  
• F. Chen, and E. H.-M. Sha, ``Loop Scheduling and Partitions for Hiding Memory Latencies,"
  in Proc. IEEE 12th International Symposium on System Synthesis}, San Jose, CA, November 1999.
  
  
• T. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Optimal Scheduling of Data-Flow Graphs Using Extended Retiming,"
  in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.
  
  
• N. L. Passos, R. Light, V. Andronache, E. H.-M. Sha, ``Design of 2-D Filters using a Parallel Processor Architecture,"
  in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.
  
  
• T. O'Neil, S. Tongsima, and and E. H.-M. Sha, ``Extended Retiming: Optimal Scheduling via a Graph-Theoretical Approach,"
  in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol. 4, pp. 2001-2004.
  
  
• S. Tongsima, T. O'Neil, and E. H.-M. Sha, ``Unfolding Probabilistic Data-flow Graphs Under Different Timing Models,"
  in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol 4, pp. 1889-1892.
  
  
• T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``A Probabilistic Performance Metric for Real-Time System Design ,"
  in Proc. 1999 7th International Workshop on Hardware Software Co-Design, Rome, Italy, May 1999, pp. 90-94.
  
  
• T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``Probabilistic Performance Estimation for Real-time Embedded Systems,"
  in Proc. 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, March, 1999, pp. 83-88.
  
  
• C. Chantrapornchai, E. H.-M. Sha, and X. S. Hu, ``Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections,"
  in Proc. IEEE 9th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March, 1999, pp. 128-131.
  
  
• Y. Tian, E. H.-M. Sha, C. Chantrapornchai, and P. M. Kogge, ``Efficient Data Placement and Replacement Algorithms for Multiple-Level Memory Hierarchy,"
  in Proc. 10th International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, October, 1998, pp. 196-201.
  
  
• F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Optimization with Data Prefetching based on Multi-dimensional Retiming,"
  in Porc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, pp. 129-134.
  
  
• F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Algorithm for Timing and Memory Operation Minimization with Register Constraint,''
  in Proc. 1998 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS), Boston, Massachusetts, October, 1998.
  
  
• C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Scheduling for Imprecise Timing Based on Fuzzy Theory,"
  in Proc. 1998 Midwest Symposium on Circuit and Systems, Notre Dame, Indiana, August, 1998.
  
  
• Andrea Leonardi, Nelson L. Passos, and Edwin H.-M. Sha, ``Nested Loops Optimization for Multiprocessor Architecture Design",
  in Proc. 1998 Midwest Symposium on Circuit and Systems,i Notre Dame, Indiana, August, 1998.
  
  
• S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos `` Optimizing Circuits with Confidence Probability using Probabilistic Retiming,"
  in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998
  
  
• D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Compile-time Priority Assignment and Re-routing for Communication Minimization in Parallel Systems,"
  in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998
  
  
• M. Sheliga, T. Yu, F. Chen, and E. H.-M. Sha, ``Graph Transformation for Communicaton Minimization Using Retiming,"
  in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998
  
  
• T. Z. Yu, F. Chen and E. H.-M. Sha, ``Loop Scheduling Algorithms for Power Reduction,"
  in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Seattle, Washington, May 1998.
  
  
• C. Chantrapornchai, S. Tongsima, E. H.-M. Sha and S. X. Hu, ``Dealing with Impreciseness in Architectural Synthesis,"
  in Proc. IASTED International Conference on Artificial Intelligence and Soft Computing, Cancun, Mexico, May, 1998.
  
  
• Y. Tian, E. H.-M. Sha, C. Chantrapornchai and P. M. Kogge, ``Optimizing Data Scheduling on Processor-In-Memory Arrays,"
  in Proc. IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.
  
  
• S. Tongsima, C. Chantrapornchai, and E. H.-M. Sha, ``Probabilistic Loop Scheduling Considering Communication Overhead,"
  in Proc. 4th Workshop on Job Scheduling Strategies for Parallel Processing, with IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.
  
  
• D. Surma and E. H.-M. Sha, ``Project-Based approach to teaching Microprocessors and their Applications,"
  in American Society for Engineering Education 1998 Spring Conference, Detroit, Michigan, April, 1998.
  
  
• K. Wang, T. Yu and E. H.-M. Sha, ``RCRS: A Framework for Loop Scheduling with Limited Number of Registers,"
  in Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, February, 1998.
  
  
• ``SCORE: An efficient technique to reduce congestion in Parallel Systems,"
  (with D. Surma and P. M. Kogge) in 10th International Conference on Parallel and Distributed Computing Systems, New Orleans, LA, October, 1997.
  
  
• ``Efficitent Data Placement for Processor-In-Memory Array Processors,"
  (with Y. Tian, C. Chantrapornchai, and P. M. Kogge) in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997.
  
  
• ``Efficitent Loop Scheduling and Pipelining for Applications with Non-uniform Loops,"
  (with S. Tongsima, C. Chantrapornchai, and N. Passos) in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997.
  
  
• ``Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time,"
  (with S. Tongsima, C. Chantrapornchai and N. Passos) in
  Proc. 1997 International Conference on Parallel Processing, Bloomingdale, Illinois, Aug., 1997.
  
  
• ``Rapid System Design Framework for Fuzzy Applications''
  (with C. Chantrapornchai, M. Sheliga and S. Tongsima) in
  Proc. IEEE 40th Midwest Symposium on Circuits and Systems, Sacramento, California, August, 1997.
  
  
• ``Efficient Communication Scheduling with Re-routing based on Collision Graphs,"
  (with D. Surma) in
  Proc. 1997 Annual International Symposium on High Performance Computing Systems, Winnipeg, Manitoba, Canada, July 10-12, 1997, pp. 483-492.
  
  
• ``Hardware/Software Codesign for Video Compression Using the EXECUBE Processor Array,"
  (with M. Sheliga and P. Kogge) in
  Proc. 1997 IEEE National Aerospace and Electronics Conference, Dayton, Ohio, July, 1997.
  
  
• ``Imprecise Task Schedule Optimization,"
  (with C. Chantrapornchai, and S. Tongsima) in
  Proc. the Sixth IEEE International Conference on Fuzzy Systems, Barcelona, Spain, July, 1997.
  
  
• ``Hybrid Static-Dynamic Communication Scheduling for Parallel Systems"
  (with D. Surma) in
  Proc. 1997 ACM Symposium on Applied Computing, San Jose, California, Feb. 1997, pp. 374-379..
  
  
• "Algorithms and Hardware Support for Branch Anticipation,"
  (with T. Yu, N. Passos and R. D.-C. Ju) in
  Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 163-168.
  
  
• "Scheduling with Confidence for Probabilistic Data Flow Graphs,"
  (with S. Tongsima, C. Chantrapornchai, and N. Passos) in
  Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 150-155.
  
  
• ``SHARP: Efficient Loop Scheduling with Data Hazard Reduction on Multiple Pipeline DSP Systems,"
  (with S. Tongsima, C, Chantrapornchai and N. Passos) in
  Proc. 1996 IEEE Workshop on VLSI Signal Processing, San Fransisco, California, November, 1996, pp. 253-262.
  
  
• ``VHDL Synthesis of Multi-Dimensional Applications: a New Approach,"
  (with N. Passos) in
  Proc. 1996 IEEE International Conference on Computer Designs, Austin, Texas, October, 1996, pp. 530-535.
  
  
• ``Polynomial-time Nested Loop Fusion with Full Parallelism,"
  (with C. Lang and N. Passos) (regular paper) in
  Proc. 1996 International Conference on Parallel Processing, August 1996, Vol 3, pp. 9-16.
  
  
• ``Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems,"
  (with D. Surma) (regular paper) in
  Proc. 1996 International Conference on Application-specific Systems, Architectures and Processors, Chicago, Illinois, August 1996, pp. 240-249.
  
  
• ``Hardware/Software Co-design for DSP Applications via the HMS Framework."
  (with Mike Sheliga) in
  Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 2, pp. 1248-1251.
  
  
• ``Optimal Communication Scheduling Based on Collision Graph Model,"
  (with D. Surma and S. Tongsima) in
  Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 6, pp. 3319-3322.
  
  
• ``Rapid Prototyping for Fuzzy Systems,"
  (with C. Chantrapornchai and S. Tongsima), in
  Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996 pp. 234-239.
  
  
• ``A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization,"
  (with N. Passos), in
  Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996, pp. 66-71.
  
  
• ``Minimization of Fuzzy Systems based on Fuzzy Inference Graph,"
  (with C. Chantrapornchai and S. Tongsima) in
  Proc. IEEE International Symposium on Circuits and Systems, Atlanta, Georgia, 1996, Vol. 4, pp. 651-654.
  
  
• ``Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications,"
  (with M. Sheliga and N. Passos) in
  Proc. 4th IEEE International Workshop on Hardware/Software Co-design, Pittsburgh, Pennsylvania, March, 1996, pp. 18-25.
  
  
• ``Push-Up Scheduling: Optimal Polynomial-Time Resource Constrained Scheduling for Multi-Dimensional Applications,"
  (with N. Passos) in
  Proc. IEEE/ACM International Conference on Computer-Aided Design, < /b> San Jose, California, November, 1995, pp. 588-591.
  
  
• ``Multi-level Partitioning and Scheduling under Local Memory Constraint," < br> (with Q. Wang and N. Passos) in
  Proc. IEEE Symposium on Parallel and Distributed Processing, (long paper), San Antonio, Texas, Dec, 1995, pp. 612-619.
  
  
• ``Fully Parallel Synchronous Circuit Design using Multi-Dimensional Interleaving,"
  (with N. Passos and L.-F. Chao) in
  Proc. IEEE Iinternational Conference on Computer Design, Austin, Texas, October, 1995, pp 440-445.
  
  
• ``Integrating Selective Fault-Tolerance into Hard Real-Time Multiprocessor Schedules," (with N. M. Sabine) in
  Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 89-94.
  
  
• ``Application-Specific Communication Scheduling on Parallel Systems,"
  (with D. R. Surma) in
  Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 137-139.
  
  
• ``Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping,"
  (with S. Tongsima and N. Passos), in
  Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 97-104.
  
  
• ``Memory-Efficient Fully Parallel Loop Transformation,"
  (with N. Passos and L.-F. Chao), in
  Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 182-185.
  
  
• ``Optimizing Synchronous Systems for Multi-dimensional Applications,"
  (with N. Passos and L.-F. Chao), in
  Proc. IEEE European Design and Test Conference, Paris, France, March, 1995, pp 54-58.
  
  
• ``Improving Self-Timed Pipeling Ring Performance Through The Addition of Buffer Loops,"
  (with Hai Zhao and N. M. Sabine), in
  Proc. IEEE Great Lakes Symposium on VLSI, March, 1995, pp 218-223 (regular paper).
  
  
• ``Bus Minimization and Scheduling of Multi-Chip Modules,"
  (with M. Sheliga), in
  Proc. IEEE Great Lakes Symposium on VLSI, Buffalo, New York, March, 1995, pp 40-45 (regular paper).
  
  
• ``Memory/Time Optimization of 2-D Filters,"
  (with N. Passos), in
  Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3223-3226.
  
  
• ``Rate-Optimal Scheduling for Cyclo-Static and Periodic Schedules,"
  (with L.-F. Chao), in
  Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3231-3234.
  
  
• ``Communication Sensitive Rotation Scheduling,"
  (with S. Tongsima and N. Passos) in
  Proc. 1994 IEEE International Conference on Computer Design, Cambridge, Massachusetts, October, 1994, pp 150-153.
  
  
• ``Full Parallelism of Uniform Nested Loops by Multi-Dimensional Retiming,"
  (with N. Passos) in
  Proc. 1994 International Conference on Parallel Processing, vol. 2, St. Charles, Illinois, August, 1994, pp. 130-133.
  
  
• ``Loop Pipelining for Scheduling Multi-dimensional Systems via Rotation,"
  (with N. Passos and S. C. Bass) in
  Proc. IEEE/ACM 1994 Design Automation Conference (nominated for the Best Paper Award, 13 nominated out of 439 papers), San Diego, California, June, 1994, pp. 485-490.
  
  
• `` Retiming and Clock Skew for Synchronous Systems," (with L.-F. Chao) in
  Proc. IEEE 1994 Interenational Symposium on Circuits and Systems, London, England, May, 1994, vol. 1, pp. 283-286.
  
  
• `` Partitioning and Retiming of Multi-dimensional Systems,"
  (with N. Passos and S. C. Bass) in
  Proc. IEEE 1994 Interenational Symposium on Circuits and Systems, London, England, May, 1994, vol. 4, pp. 227-230.
  
  
• ``Global Node Reduction of Linear Systems Using Ratio Analysis,"
  (with M. Sheliga) in
  Proc. IEEE Seventh International Symposium on High-Level Synthesis, Niagara-on-the-Lake, Canada, May, 1994, pp. 140-145.
  
  
• ``Schedule-Based Multi-Dimensional Retiming on Data-Flow Graphs,"
  (with N. Passos and S. C. Bass) in
  Proc. 1994 International Parallel Processing Symposium, Cancun, Mexico, April, 1994, pp. 195-199.
  
  
• `` Rotation Scheduling: A Loop Pipelining Algorithm,'' (with L.-F. Chao and A. LaPaugh) in
  Proc. 30th ACM/IEEE Design Automation Conference, (nominated for the Best Paper Award), Dallas, Texas, June 1993, pp. 566-572.
  
  
• ``Rate-Optimal Static Scheduling for DSP Data-Flow Programs", (with L.-F. Chao), in
  Proc. IEEE Third Great Lakes Symposium on VLSI, March 1993, pp 80-84.
  
  
• ``Efficient Retiming and Unfolding," (with L.-F. Chao) in
  Proc. 1993 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Minneapolis, Minnesota, April, 1993, pp. I421-I424.
  
  
• ``Static Scheduling of Uniform Nested Loops," (with L.-F. Chao), in
  Proc. 7th International Parallel Processing Symposium, Newport Beach, California, April, 1993, pp.254-258.
  
  
• ``Maintaining Bipartite Matchings in the Presence of Failures,'' (with K. Steiglitz), in
  Proc. of 7th International Parallel Processing Symposium, (Long Paper), Newport Beach, California, April, 1993, pp. 57-64.
  
  
• ``Unified Static Scheduling on Various Models," (with L.-F. Chao), in
  Proc. 1993 International Conference on Parallel Processing, St. Charles, Illinois, August 1993, pp. II 231-235.
  
  
• ``Retiming and Unfolding Data-Flow Graphs," (with L.F. Chao),
  Proc. 1992 International Conference on Parallel Processing, St. Charles, Illinois, August 1992, pp. II 33-40.
  
  
• ``Scheduling Cyclic Data-Flow Graphs by Retiming with Resource Constraints," (with L.F. Chao and A. LaPaugh),
  ACM/IEEE Sixth International Workshop on High-Level Synthesis, Dana Point, California, November 1992, pp. 111-134.
  
  
• ``Algorithms for Min-Cut Linear Arrangements of Outerplanar graphs" (with L.F. Chao),
  Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May 1992, pp. 1851-1854.
  
  
• ``An Error-Detectable Array for All-Substring Comparison,"
  Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May 1992, pp 2941-2944.
  
  
• ``Run-Time Error Detection in Arrays Based on the Data-Dependency Graph," (with K. Steiglitz),
  Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San. Francisco, March 1992, Vol. 5, pp. 625-628.
  
  
• ``Unfolding and Retiming Data-Flow DSP Programs for RISC Multiprocessor Scheduling" (with L.F. Chao),
  Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San Francisco, California, March 1992, Vol. 5, pp. 565-568.
  
  
• ``Efficient Distributed Reconfiguration for Binary Trees on Diogenes Model," (with L.F. Chao),
  Proc. 1992 Int'l Phoenix Conf. on Computers and Communications, Scottsdale, Arizona, April 1992, pp. 464-471.
  
  
• ``Optimizing Synchronous Systems via Retiming and Unfolding," (with L.F. Chao),
  Tau 1992: 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
  
  
• ``Explicit Constructions for Reliable Reconfigurable Array Architectures,'' (with K. Steiglitz),
  Proc. Third IEEE Symposium on Parallel and Distributed Processing, < /b> Dallas, Texas, Dec. 1991, pp. 640-647
  
  
• ``Planar Linear Arrangements for Outerplanar graphs," (with L.F. Chao),
  Proc. 1991 Second Great Lakes Computer Science Conference, Kalamazoo, Michigan, Oct. 1991.
  
  
• ``Design for Easily Applying Test Vectors to Improve Delay Fault Coverage,'' (with L.F. Chao),
  Proc. 1991 IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, Nov. 1991, pp. 500-503.
  
  
• ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,'' (with K. Steiglitz),
  Proc. 1991 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Toronto, Canada, May 1991, Vol. 2, pp. 1001-1004.
  
  

Dr. Edwin Sha
Department of Computer Science
Erik Jonsson School of Engineering and Computer Science
Box 830688, MS EC 31
University of Texas at Dallas
Richardson, TX 75083-0688
Voice: (972) 883-4193
Fax...: (972) 883-2349

edsha@utdallas.edu

Revised - Aug. 10, 2005.