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Edwin (Hsing Mean) SHA




Professor
Department of Computer Science
University of Texas at Dallas
MS EC 31, Richardson, TX 75083-0688
Tel. (972) 883 4193
Fax: (972) 883 2349
Email: edsha@utdallas.edu
URL: http://www.utdallas.edu/~edsha

Edwin Sha received the B.S.E. degree in computer science and information engineering from National Taiwan University, Taipei, Taiwan, in 1986; he received the M.A. and Ph.D. degree from the Department of Computer Science, Princeton University, Princeton, NJ, in 1991 and 1992, respectively. From August 1992 to August 2000, he was with the Department of Computer Science and Engineering at University of Notre Dame, Notre Dame, IN. He served as the Associate Chair and the Graduate Director of the department at Notre Dame from 1995 to 2000. Since 2000, he has been a tenured full professor in the Department of Computer Science at the University of Texas at Dallas (UTD). He served as the Head of Computer Science Division in 2001 and the coordinator for Computer Systems Group at UTD.


He has published more than 230 research papers in refereed international conferences and premier journals. He served in the program committees of numerous conferences and editors of many journals including IEEE Transactions on VLSI Systems, IEEE Transactions on Signal Processing, Journal of Embedded Computing, Journal of VLSI Signal Processing, etc. He received Oak Ridge Association Junior Faculty Enhancement Award, Notre Dame CSE Teaching Award, NSF CAREER Award, NSF ITR grant, Microsoft Trustworthy Curriculum Award and NSFC Overseas Distinguished Young Scholar (B). He served as the program chairs or general chairs for many international conferences such as Great Lakes Symposium on VLSI (GLSVLSI) 1994, Parallel and Distributed Computing (PDCS) 2000, PDCS 2001, Parallel and Distributed Embedded Systems (PDES) 2005, Embedded and Ubiquitous Computing (EUC) 2006, Embedded Software Optimizations (ESO) 2006, EUC 2007, ESO 2007, International Symposium on Embedded Computing (SEC) 2008. His research has been supported by NSF (CAREER, ITR, EIA, IIS), Texas Instruments, AT&T, Texas Advanced Research Program, Microsoft Research, etc.


He has graduated 13 PhD students. Three of them received UTD ECS Best PhD Dissertation Awards in 2003, 2005 and 2007 respectively. His research goal is to efficiently design parallel, distributed and heterogeneous embedded architectures with the guarantee to satisfy the given requirements such as timing, power, memory-size, cost, security, etc. He has been developing new techniques that optimize timing performance and minimize power consumption for DSP applications and computer security applications considering multiple data memory modules and strict code-size constraint in embedded processors. Many optimization algorithms have been developed such as hardware/software combined security defender, code-size reduction, multi-dimensional (MD) retiming, MD rotation, MD interleaving, nest-loop pipelining, integrated design space minimization, fast intrusion detection hardware, and intelligent data/memory management and partitioning. After moving to UTD, he has been studying efficient routing and partitioning in mobile ad-hoc networks. The detailed information can be found on the web at
http://www.utdallas.edu/~edsha.

Research Interests and Specialties

Embedded Software and Systems, Computer and Network Security, Parallel Architectures and Systems, High-performance and Low-Power Real-Time Systems, Network Architectures, Compilers, Application Specific VLSI Design, Operating Systems, High-Level Synthesis.
Citizenship:
USA
Education


Ph.D. Computer Science Princeton University Oct. 1992
Thesis title: Real-Time Fault Tolerance for Array Architectures
Advisor: Prof. Kenneth Steiglitz
M.A. Computer Science Princeton University Jan. 1991
B.S.E. Computer Science National Taiwan University June 1986
(GPA: 3.9/4.0, Book Coupon Awards, five times)

Professional Experience

Aug. 00 - Present Professor (Tenured) Dept. of Computer Science
    University of Texas at Dallas, TX
     
Jan. 02 - Oct. 2004 Coordinator Computer Systems Group
    University of Texas at Dallas, TX
     
Aug. 98 - Aug. 00 Associate Professor (Tenured) Dept. of Computer Science & Engr.
  Associate Chair University of Notre Dame, IN
     
May 95 - Aug. 98 Assistant Professor Dept. of Computer Science & Engr.
  Associate Chair University of Notre Dame, IN
     
Aug. 92 - May 95 Assistant Professor Dept. of Computer Science & Engr.
    University of Notre Dame, IN
     
Sep. 88- July 92 RA and TA Dept. of Computer Science
    Princeton University, NJ
     
Aug. 86- May 88 System Programmer Marine Corps, Taiwan

Membership


ISCA, ACM and The Institute of Electrical and Electronics Engineers (IEEE).

Courses taught and designed since August 1992


Computer and Network Security, Information Security, Parallel Architectures and Systems, Synthesis and Optimization of High-Performance Systems, Data Structures, VLSI Processor Arrays, Principles of Parallel Computing, Specialized Parallel Architectures, Operating Systems Principles, Automata.

Graduate Students Advised (as their major thesis advisor)


  1. Jason Xue, Ph.D. degree, 2007, Ph.D. Dissertation Title: Memory and Parallelism Optimization for Embedded Systems. Received the 2007 UTD ECS The Best PhD Dissertation Award.

  2. Meikang Qiu, Ph.D. degree, 2007, Ph.D. Dissertation Title: Time and Power Optimization for Heterogeneous Parallel Embedded Systems.

  3. Meilin Liu, Ph.D. degree, 2006, Ph.D. Dissertation Title: Loop Transformation Techniques Considering Timing and Memory Optimization for Embedded Systems.

  4. Kevin Chen, Ph.D. degree, 2006, Ph.D. Dissertation Title: Efficient Network Architectures and Switch Fabrics for Packet Routing.

  5. Zili Shao, Ph.D. degree, 2005, Ph.D. Dissertation Title: High Performance, Low Power and Secure Embedded Systems. Received the 2005 UTD ECS The Best PhD Dissertation Award.

  6. Bin Xiao, Ph.D. degree, 2003, Ph.D. Dissertation Title: Dynamic Techniques for Constant Change Networks.

  7. Qingfeng Zhuge, Ph.D. degree, 2003, Ph.D. Dissertation Title: Timing and Memory Optimization for Embedded Systems. Received the 2003 UTD ECS The Best PhD Dissertation Award.

  8. Timothy O'Neil, Ph.D. degree, 2002, Ph.D. Dissertation Title: Techniques for Optimizing Loop Scheduling.

  9. Virgil Andronache, Master degree, 2000, Thesis Title: Intelligent Page Placement and Replacement on Multiple Level Memory Systems.

  10. JiangFeng Ding, Master degree, 2000, Thesis Title: Application Specific Image Compression for Virtual Conferencing.
  11. Fei Chen, Master degree, 2000, Thesis title: Intelligent Algorithms for Hiding Memory Latencies.
  12. Joy Chantrapornchai, Ph.D. degree, 1999, Ph.D. Dissertation Title: System Level Synthesis Considering Impreciseness Based on Fuzzy Theory.

  13. Sissadas Tongsima, Ph.D. degree, 1999, Ph.D. Dissertation Title: Loop Scheduling for Applications with Fixed or Probabilistic Timing Information.

  14. Milind Saraph, Master degree, 1998, Thesis Title: Distributed File Systems: An Empirical Study.

  15. David Surma, Ph.D. degree, 1998, Ph.D. Dissertation Title: Collision Graph Based Communication Scheduling and Applications.

  16. Kaisheng Wang, Master Degree, 1998, Thesis Title: Register Constrained Rotation Scheduling.

  17. Ted Zhihong Yu, Master Degree, 1997, Thesis Title: Algorithms and Hardware Support for Multi-Dimensional Branch Anticipation.

  18. Michael Sheliga, Ph.D. Degree, 1997, Ph.D. Dissertation Title: Efficient High Level Synthesis Using Hardware/Multi-Software Co-Design and Communication Minimization.

  19. Nelson Passos, Ph.D. Degree, 1996, Ph.D. Dissertation Title: The Multi-Dimensional Retiming Framework.

  20. Nicole Sabine, Master Degree, 1995, Thesis Title: Selectively Fault-Tolerant, Hard Real-Time Multiprocessor Scheduling.
  21. Yvonne (YuHong) Wang, Master Degree, 1995, Thesis Title: Scheduling via Node Replication for Parallel Systems.
  22. Sissadas Tongsima, Master Degree, 1995, Thesis Title: Communication Sensitive Scheduling for Parallel systems.
  23. Jenny (QingYan) Wang, Master Degree, 1995, Thesis Title: Memory Constrained Partitioning and Scheduling for Multi-dimensional Applications.
  24. John Swadener, Master Degree, 1994, Thesis Title: A Simulation Environment for Automatic Partitioning and Scheduling of Parallel Programs Based on Simulated Annealing.

Undergraduate Students Advised


  1. Roger Patrick Gorman and Ronald Setia, 1999 and 2000, Research Project: Java Parallel Virtual Machines.
  2. Sam Ruppert and Richard Wiseman, 1999 and 2000, Research Project: Virtual Network Chat with Animated Face.
  3. Melissa Layton, Vincent Oh, 1999 and 2000, Research Project: Virtual Mobile Dog: An example of Mobile Agent.
  4. Ronald Setia, Mohamed Helmy, and Roger Gorman, 1999, Research Project: Simulator for Java Virtual Machine and Pipelined JVM.

  5. Ryan Carlson and Michael Dreznes, 1998 and 1999, Research Project: Java Virtual Conference.

  6. Dominic Fahey and Clinton Grady,1998 and 1999, Research Project: Multiple-thread Real-Time Java Based Web Camera.

  7. Joseph Bishay and Donald Reinhart, 1997, Research Project: Pegasus: tools for collaborating and communicating for multiple users.

  8. Nathan Isley, CSE, 1997, Research Project: Virtual Friend based on Java.

  9. Becky Saydak, CSE, 1995, Research Project: Real-Time Multiprocessor Scheduling for Fault-tolerance.

  10. Thomas Aranda, CSE, 1995, Research Project: Simulation Tools for Parallel Systems.

  11. Dan Cieslak, CSE, 1995 and 1996, Research Project: Efficient Parallel Programming.

Graduate Students being Currently Advised


  1. Cathy Xu, Ph.D. Student, Research Project: Optimizing Scheduling and Inter-Cluster Connection for Application-Specific DSP Proessors .

  2. Jingtong (Aaron) Hu, Ph.D. Student, Research Project: Memory Issues of Parallel Embedded Systems.

  3. Yi He, Ph.D. Student, Research Project:Reliability-Driven Scheduling for Heterogeneous Embedded Systems.

  4. Daniel Lorts, Ph.D. Student, Research Project: Reconfigurable Computing.

  5. Ping Mao, Ph.D. Student, Research Project: Optimizations for Application Specific Communications .

Grants


  1. Oak Ridge Associated Universities, Timing Optimization for Multi-Dimensional Scientific Applications, Principal Investigator, $10,000, June 1994 - May 1995.

  2. NSF Cornell Theory Center, 90 service units for KSR and IBM SP1, Principal Investigator, August 1993 - January 1994.

  3. NSF CAREER Award, High-Level Design Methodologies for Time-Optimal and Memory-Optimal Systems, Principal Investigator, MIPS 95-01006, $139,000, (the amount from NSF), June 1995 - May 1999.

  4. NSF Pittsburgh Supercomputing Center, 554 Service Units for Cray C90 and Cray T3D, Principal Investigator, September 1995 - September 1996.

  5. NSF National Center for Supercomputing Applications, 25 SU Hours for CM5, Principal Investigator, August 1995 - January 1996.

  6. NSF Cornell Theory Center, 100 service units for IBM SP2, Principal Investigator, August 1995 - January 1996.

  7. NSF Equipment Grant, Principal Investigator, MIPS 95-01006, $50,000, May 1996 - May 1999.

  8. NSF, Co-PI (with Peter Kogge, Jay Brockman, Steven Bass, and Danny Chen), Pursuing A Petaflop: Point Designs for 100 TF Computers Using PIM Technologies, NSF ACS 96-12028, $100,000, April 1996 - May 1997.

  9. NSF, Co-PI (with Nelson Passos), Architecture support and code generation for general nested loops with fine-grain parallelism, MIP-9704276, $240,000, July 1997 - June 2000.

  10. DARPA ITO (through JPL and NASA), Co-PI (with Peter Kogge, Steven Bass, Jay Brockman, Andy Lumnsdaine and Vincent Freeh), A Hybrid Technology MultiThreaded Architecture for Petaflops Computing, JPL Award No. 961097, $604,200, May 1997 - June 1999.

  11. AT&T, PI, Communication Bandwidth Reduce Techniques & IP video Phone, Award No. A-98-11-00002, $25,000, May 1998 - August 1999.

  12. AT&T, PI, Video Chat and Bandwidth Reduction Techniques, $25,000, September 1999 - May 2001.

  13. Texas Instruments, PI, Hardware/Software Co-Designs for DSP and Communications, Lab. Equipments, $49,514, November, 2000.

  14. Xilinx, PI, Embedded Systems Designs, Lab. Equipments, $43,390, January, 2001.

  15. NSF, Co-PI (with I-L Yen, F. Bastani, Y. Deng, L. Khan), EIA-0103709, A Distributed Component Repository for Rapid Synthesis of Adaptive Real-Time Systems, $499,866, September 2001 - August 2004.

  16. ARP, PI, Algorithms on High-Level Synthesis and Optimization for High-Performance Systems, $96,000, Jan. 2002 - Aug. 2004.

  17. NSF, PI, CCR-0309461, Design Space Exploration and Synthesis for Multiple-Mode Embedded Systems, $210,000 plus UTD Matching, Sept. 2003 - Aug. 2007, NSF ITR grant.

  18. Microsoft, PI, The Development of Trustworthy Computing Course, $50,000, Since Jan. 2005, Unrestricted gift account.

  19. Hong Kong Polytech University, Academic Visiting Scholar Grant, HK$30,000 plus travel expense, May 2004.

  20. Wind River, PI, Embedded Systems Research, Wind River University Program Grant, Platform Software for Network Equipment, and Development tools for VxWorks, $100,000, September 2004.

  21. Altera Corporation, PI, Embedded Systems Design and Optimization, Altera University Program Grant, QUARTUS II development suites, $26,170, Jan. 2005.

  22. UTD, Co-PI (with W. Wu, F. Qiu), Efficient Spatial-Temporal Analysis of Environment and Public Health Related Data, $60,000, May 2005 - Aug. 2006.

  23. Hong Kong, Research Grant Council, CO-PI (with Bin Xiao), RGC PolyU A-PA2F, To Provide Network Security from the Prevention of Buffer Overflows to the Early-stage Detection of DDoS Attacks, HK $150,000, Aug. 2005 - July 2007.

  24. NSF, Co-PI (with W. Wu, F. Qiu), NSF IIS-0513669, Efficient Spatial-Temporal Analysis of Environment and Public Health Related Data, $397,504, Sept. 2005 - Aug. 2008.

  25. Hong Kong, Research Grant Council, Competitive Earmarked Research Grant (CERG), CO-PI (with Bin Xiao), CERG B-Q02S, Early Detection and Effective Counteraction of DDoS attacks at the Victim Server Side, HK $534,000, Jan. 2007 - Dec. 2009.

  26. Altera Corporation, PI, Embedded Systems Education and Research, Altera University Program Grant, QUARTUS II development suites, $22,000, Dec. 2006.

  27. NSFC, PI, NSFC-60728206, Exploring Integrated Optimizations for Embedded Software on Parallel Systems, Overseas Distinguished Young Scholar (B), National Natural Science Foundation of China, RMB$400,000, 2007 - 2010.

  28. Hong Kong, Research Grant Council, Competitive Earmarked Research Grant (CERG), CO-PI (with Zili Shao), CERG B-Q60B, Compiler-Assisted Scheduling Techniques for Energy Saving on Parallel Embedded Systems, HK $648,000, Jan. 2008 - Dec. 2010.

  29. NSF, PI, SRS: Optimization for Heterogeneous Embedded Software Considering Hardware Platform, $271,868, Sept. 2008 - Aug. 2011, submitted.

  30. NSF, PI, On Challenges of Maximizing Parallelism and Hiding Memory Latency Overhead for Multi-Cores, $316,884, Sept. 2008 - Aug. 2011, submitted.

  31. ARP, PI, On Parallel Embedded Systems: Challenges and Optimizations, $114,000, . June, 2008 - May 2010, submitted.

Professional Activities and Awards


  1. Microsoft Trustworthy Computing Curriculum Development Award, 2005.

  2. Recently Invited Speeches:
    City University of Hong Kong, November 2007, University of Electronic Science and Technology of China, July 2007, Beihang University July 2007, Shanghai Jiaotong University, July 2007, Shandong University, July 2007, Renmin University of China, June 2006, Suzhou University, June 2006, Shandong University, June 2006, National Taiwan University, May 2006, Shandong University May 2005, Jiangsu University May 2005, Nanjing University December 2004, Zhijiang University December 2004, Jiangsu University December 2004, Shanghai Jiaotong University December 2004, Tsinghua University October 2004, National Taiwan University October 2004, Hong Kong Polytechnic University May 2004, Shanghai Jiaotong University May 2004, Tsinghua University March 2003.

  3. Keynote/Distinguished Speeches:
    Arizona State University, March 2007.
    2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC 2005), Nagasaki, Japan, December 2005.
    Emerging Information Technology Conference (EITC 2005), Taipei, Taiwan, August 2005.
    The Ninth Workshop on Compiler Techniques for High-Performance Computing, Taipei, Taiwan, March 2003.

  4. Overseas Distinguished Young Scholar (B), National Natural Science Foundation of China (NSFC), RMB$400,000, 2007 - 2010.

  5. Member of Embedded Systems Expert Committee, Chinese Institute of Electronics, June 2006 - Present.

  6. Visiting Professor, National Taiwan University, Taiwan, Sponsered by National Education Ministry, May 2006.

  7. Specially Appointed Visiting Professor, Shandong University, Jinan, Shandong, China, 2006.

  8. Guest (Honorary) Professor, Shandong University, Jinan, Shandong, China, 2005 - Present.

  9. Part-Time PhD Advising Professor, Shandong University, Jinan, Shandong, China, 2006 - Present.

  10. Guest (Honorary) Professor, Shanghai Jiaotong University, Shanghai, China, 2004 - Present.

  11. General Committee Co-Chair of the 2008 International Workshop on Embedded Software Optimization (ESO 2008), Shanghai, China, December 2008.

  12. General Committee Co-Chair of the 5th 2008 IEEE International Symposium on Embedded Computing (SEC 2008), Beijing, China, October 2008.

  13. General Committee Co-Chair of the 2007 International Workshop on Embedded Software Optimization (ESO 2007), Taipei, Taiwan, December 2007.

  14. General Chair of the 2007 IFIP International Conference on Embedded And Ubiquitous Computing (EUC 2007), Taipei, Taiwan, December 2007.

  15. Steering Committee Chair of the International Workshop on Embedded Software Optimization (ESO).

  16. Program Committee Chair of the 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC 2006), Seoul, Korea, August 2006.

  17. General Committee Co-Chair of the 2006 International Workshop on Embedded Software Optimization (ESO 2006), Seoul, Korea, August 2006.

  18. General Committee Co-Chair of the First International Workshop on Security in Ubiquitous Computing (SecUbiq-05) in conjunction with EUC 2005, Nagasaki, Japan, Dec. 2005.

  19. General Committee Co-Chair of the 1st International Workshop on Parallel and Distributed Embedded Systems (PDES) in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005.

  20. Evaluation Committee, The National Science and Technology Program for Systems-on-Chip (NSTPSoC), Republic of China, Taiwan, 2004.

  21. Program Committee Chair of the 14th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), Texas, August 2001.

  22. Program Committee Chair (with Prof. Ghulam M. Chaudhry) of the 13th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), Las Vegas, Nevada, August 2000.

  23. Teaching Award of the Department of Computer Science and Engineering, University of Notre Dame, 1998.

  24. Guest Editor, Special Issue on Embedded System Design & Optimization, Journal of Embedded Computing (JEC), 2007 - 2008.

  25. Guest Editor, Special Issue on Ubiquitous Computing, International Journal on Pervasive Computing and Communications (JPCC), 2007 - 2008.

  26. Guest Editor, Special Issue on Design and Programming of Signal Processors for Multimedia Communication, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), 2006 - 2007.

  27. Editor, Journal of Embedded Computing (JEC), 2003 - Present.

  28. Editor, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), 2000 - Present.

  29. Editor, IEEE Transactions on Signal Processing, handling submissions related to VLSI Systems and Programming Systems, 1999 - 2001.

  30. Guest Editor (with Prof. Anantha Chandrakasanon at MIT), Special Issue on low power VLSI systems, IEEE Transactions on VLSI Systems, published in Dec. 1998.

  31. Editor, Journal of Circuits, systems and Computers, 1998.

  32. NSF CAREER Award, High-Level Design Methodologies for Time-Optimal and Memory-Optimal Systems, 1995.

  33. 1994 Junior Faculty Enhancement Award of Oak Ridge Associated University in Mathematics/Computer Science.

  34. An Honorable alternate of 1993 Junior Faculty Enhancement Award of Oak Ridge Associated University in Mathematics/Computer Science.

  35. Steering Committee of the 2008 IFIP/IEEE International Conference on Embedded And Ubiquitous Computing (EUC 2008), Shanghai, China, December 2008.

  36. International Advisory Committee of the 2008 International Conference on Security Technology (SecTech 2008), Hainan, China, December 2008.

  37. International Advisory Committee of the IEEE 5th International Joint Conference on Computer Science and Software Engineering (JCSSE 2008), Kanchanaburi, Thailand, May 2008.

  38. International Advisory Board of the International Conference on Information Security and Assurance (ISA 2008), Busan, Korea, April 2008.

  39. International Advisory Committee of the 2007 international Workshop on Intelligent Systems and Smart Home (WISH 2007), Niagara Falls, Canada, August 2007.

  40. Steering Committee of the International Workshop on Interactive Multimedia & Intelligent Services in Mobile and Ubiquitous Computing 2007 (IMIS2007), Seoul, Korea, April 2007.

  41. Advisory Committee of the International Conference on Information Security and Computer Forensics (ISCF 2006), Chennai, India, December 2006.

  42. Program Committee of the 2009 IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2009), Innsbruck, Austria, Feb. 2009.

  43. Program Committee of the The 10th International Conference on Computer Science & Informatics (CSI 2008), Shenzhen, China, December 2008.

  44. Program Committee of the 2008 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2008), Atlanta, Georgia, USA, October 2008.

  45. Program Committee of the 6th Bi-Aannual IFIP Conference on Distributed and Parallel Embedded Systems (DIPES 2008), Milano, Italy, September 2008.

  46. Program Committee of the IEEE International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation" (IC-SAMOS), Sammos, Greece, July 2008.

  47. Program Committee of the 8th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP-2008), Cyprus, June 2008.

  48. Program Committee of the 27th IEEE Real-Time Systems Symposium (RTSS 2007), Tucson, Arizona, December 2007.

  49. Program Committee of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2007), Cambridge, Massachusetts, November 2007.

  50. Program Committee of the 2007 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 2007.

  51. Program Committee of the Third International Symposium on Information Assurance and Security (IAS07), Manchester, United Kingdom, August 2007.

  52. Program Committee of the IEEE International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation" (IC-SAMOS), Sammos, Greece, July 2007.

  53. Program Committee of the 7th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP-2007), Hangzhou, China, June 2007.

  54. Program Committee of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), Rio de Janeiro, Brazil, December 2006.

  55. Program Committee of the 18th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2006), Dallas, Texas, November 2006.

  56. Program Committee of 2006 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2006), Seoul, Korea, October 2006.

  57. Program Committee of the 5th Bi-Aannual IFIP Conference on Distributed and Parallel Embedded Systems (DIPES 2006), Braga, Portugal, October 2006.

  58. Program Committee of the IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC2006), Taichung, Taiwan, June 2006.

  59. Program Committee of the 8th Asia Pacific Web Conference (APWeb), Harbin, China, January 2006.

  60. Program Committee of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2005), Phoenix, Arizona, November 2005.

  61. Program Committee of the 6th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP-2005), Melbourne, Australia, October 2005.

  62. Program Committee of the 18th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), Las Vegas, NV, Sept. 2005.

  63. Program Committee of Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2005), New York, New York, September 2005.

  64. Program Committee of 2005 High Performance Computing and Simulation (HPC&S) Conference, Riga, Latvia, June 2005.

  65. Program Committee of the First International Workshop on Security in Networks and Distributed Systems (SNDS 2005) in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005.

  66. Program Committee of Information Assurance and Security (IAS 2005), in conjunction with IEEE International Conference on Information Technology: Coding and Computing (ITCC 2005), Las Vegas, Nevada, April 2005.

  67. Program Committee of The International Conference on Information Systems- New Generations (ISNG), Las Vegas, NV, April, 2005.

  68. Program Committee of The First International Conference on Embedded Software and Systems (ICESS' 04), Hangzhou, China, Dec. 2004.

  69. Program Committee of The International Conference on Information Systems- New Generations (ISNG), Las Vegas, NV, November, 2004.

  70. Program Committee of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems, MIT, Cambridge, MA, November, 2004.

  71. Program Committee of the ACM/IEEE International Conference on Hardware/Software Codesigns and System Synthesis (CODES+ISSS 2004), Stockholm, Sweden, Sept., 2004.

  72. Program Committee of the 17th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), San Francisco, CA, Sept. 2004.

  73. Program Committee of The First International Workshop on Networked Embedded Computing (NEC 2004), in conjunction with The 2004 International Conference on Parallel Processing (ICPP 2004), Montreal, Canada, August, 2004.

  74. Program Committee of The International Conference on Embedded and Ubiquitous Computing (EUC-04), Aizu, Japan, August, 2004.

  75. Program Committee of 2004 High Performance Computing and Simulation (HPC&S) Conference, Magdeburg, Germany, June 2004.

  76. Program Committee of Information Assurance and Security (IAS 2004), in conjunction with International Conference on Information Technology: Coding and Computing (ITCC 2004), Las Vegas, Nevada, April 2004.

  77. Program Committee of the International Workshop of Embedded Computing (EC-04) in conjunction with the IEEE 24th International Conference on Distributed Computing Systems (ICDCS 2004), Tokyo, Japan, March 2004.

  78. Program Committee of the 15th IASTED International Conference on Parallel and Distributed Computing and Systems, Marina del Rey, California, November, 2003.

  79. Program Committee of the 2003 International Conference on Parallel Processing (ICPP 2003), Kaohsiung, Taiwan, October 2003.

  80. Program Committee of the ACM/IEEE International Conference on Hardware/Software Codesigns and System Synthesis (CODES+ISSS 2003), Newport Beach, California, October 2003.

  81. Program Committee of the 2003 The Seventh International Conference on Computer Science and Informatics (CSI 2003), Cary, North Carolina, September 2003.

  82. Program Committee of The 2nd Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing (SPDSEC 03), in conjunction with PACT-03, New Orleans, Louisiana, September 2003.

  83. Program Committee of the 16th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), Reno, Nevada, August, 2003.

  84. Program Committee of the 2003 International Symposium on Parallel Processing and Applications (ISPA 2003), Aizu-Wakamatsu City, Japan, July, 2003.

  85. International Program Committee of 2003 High Performance & Large Scale Computing (HP&LSC) Conference, Nottingham, UK, June, 2003.

  86. Program Committee of the 5th IEEE International Conference on Algorithms and Architecture for Parallel Processing (ICA3PP2002), Beijing, China, December 2002.

  87. Program Committee of the 14th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November, 2002.

  88. Program Committee of the 15th ACM/IEEE International Symposium on System Synthesis (ISSS 2002), Kyoto, Japan, October, 2002.

  89. Program Committee of the Workshop on Embedded System Codesign, San Jose, California, September, 2002.

  90. Program Committee of the 15th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), Louisville, Kentucky, September, 2002.

  91. Program Committee of the 13th IASTED International Conference on Parallel and Distributed Computing and Systems, November, 2001.

  92. Program Committee of the 4th IEEE International Conference on Algorithms and Architecture for Parallel Processing (ICA3PP2000), Hong Kong, December 2000.

  93. Program Committee of the 12th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, November, 2000.
  94. Program Committee of the 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November, 1999.

  95. Program Committee of the IEEE Seventh International Symposium on the Frontiers of Massively Parallel Computation, Annapolis, Maryland, February, 1999.

  96. Program Committee of the IEEE/ACM 11th International Symposium on System Synthesis (ISSS 1998), Hsinchu, Taiwan, December, 1998.

  97. Program Committee of the 10th International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, October, 1998.

  98. Program Committee of the IEEE/ACM 10th International Symposium on System Synthesis, Antwerp, Belgium, September, 1997.

  99. Program Committee of the IEEE Seventh Great Lakes Symposium on VLSI, Urbana, Illinois, March, 1997.

  100. Program Committee of the IEEE/ACM Ninth International Symposium on System Synthesis, La Jolla, California, November, 1996.

  101. Program Committee of the IEEE Sixth International Symposium on the Frontiers of Massively Parallel Computation, October, 1996.

  102. Program Committee of the IEEE Sixth Great Lakes Symposium on VLSI, Ames, Iowa, March, 1996.

  103. Program Committee of the IEEE Fifth Great Lakes Symposium on VLSI, Buffalo, New York, March, 1995.

  104. Program Committee Co-Chair (with Prof. John Uhran) of the IEEE Fourth Great Lakes Symposium on VLSI, March, 1994, Notre Dame, Indiana. (Co-sponsored by IEEE Computer society, and IEEE Circuits and Systems Society and in cooperation with ACM).

  105. Reviewer for Proposals submitted to NSF Microelectronic systems Architecture Program and Design, Tool and Test Program.

  106. Reviewer for many journals including IEEE Transactions on VLSI Systems, IEEE Transactions on CAD, Journal of VLSI Signal Processing, IEEE Transactions on Circuits and Systems, IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Signal Processing, etc.

University Services


  1. UTD Committee on Academic Integrity, University of Texas at Dallas, 2006 - 2008.

  2. ECS Dean's Advisory Committee on Continuity, ECS, University of Texas at Dallas, 2006 - Present.

  3. School Personnel Review Committee, ECS, University of Texas at Dallas, 2004 - 2006.

  4. Committee on Effective Teaching, University of Texas at Dallas, Representative member for ECS school, 2003 - 2005.

  5. Coordinator, Computer Systems Group, Department of Computer Science, University of Texas at Dallas, Jan. 2002- 2004.

  6. Committee on Academic Affairs, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, 2003 - 2005.

  7. Committee on Effective Teaching, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, 2002 - 2005.

  8. University Internal Research Committee, University of Texas at Dallas, 2002 - 2004.

  9. Committee on Educational Policy, University of Texas at Dallas, August 2001 - August 2003.

  10. Founding Director, Hardware/Software Co-Design Lab for DSP and Communications, University of Texas at Dallas, 2000.

  11. Founding Co-director, Computer and Network Architecture Lab. University of Texas at Dallas, 2000.

  12. Associate Chair of the Department of Computer Science, University of Texas at Dallas, May 2001 - Dec. 2001.

  13. Chair, Ph.D. Degree Program Committee of the Department of Computer Science, University of Texas at Dallas, Sept. 2000 - August 2001.

  14. Associate Chair of the Department of Computer Science and Engineering, University of Notre Dame, August 1995 - August 2000.

  15. Graduate Committee of the Department of Computer Science and Engineering, University of Notre Dame, October 1992 - August 2000.

  16. College Council, Engineering College, University of Notre Dame, August 1995 - May 1997.

  17. Honesty Committee of the Department of Computer Science and Engineering, University of Notre Dame, August 1994 - August 2000.

Patents

  1. ``Parallel Variable Length Pattern Matching Using Hash Table," C Xue, E. H.-M. Sha, M. Qiu, Q. Zhuge, U. S. Patent, Serial No. 11/307,864.

  2. ``Minimize Energy Consumption Using Optimal Voltage Assignment Algorithm," M. Qiu, E. H.-M. Sha, C. Xue, Q. Zhuge, U. S. Patent, Serial No. 11/307,924.

Books, Book Chapters, Special Issues

  1. Embedded and Ubiquitous Computing, Tei-Wei Kuo, Edwin Sha, M. Guo, L. T. Yang, and Z. Shao, ISBN-10: 3-540-77091-7, Springer-Verlag, 2007.

  2. Embedded and Ubiquitous Computing, Edwin Sha, S. Han, C. Xu, M. Kim, L. T. Yang, and B. Xiao, ISBN: 3-540-36679-2, Springer-Verlag, 2006.

  3. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, ``Optimizing Nested Loops with Loop Distribution and Loop Fusion," Book Chapter in Embedded Systems: Status and Perspective, American Scientific Publishers, 2007.

  4. Special Issue on Embedded System Design & Optimization, Journal of Embedded Computing (JEC), Guest Editor, 2007-2008.

  5. Recent Advances in Ubiquitous Computing, International Journal on Pervasive Computing and Communications (JPCC), Guest Editor, Vol. 4, No. 2, 2008.

  6. Special Issue on Design and Programming of Signal Processors for Multimedia Communication, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Guest Editor, 2006 - 2007.

  7. Special Issue on Low Power VLSI Systems, IEEE Transactions on VLSI Systems, Guest Editor, 1998.

Refereed Publications

Regular Journal Papers Published or Accepted for Publication

  1. C. Xue, Q. Zhuge, Y. He, M. Liu, and E. H.-M. Sha, ``Variable Length Pattern Matching for Hardware Network Intrusion Detection System," Accepted in Journal of Signal Processing Systems for Signal, Image, and Video Technology, Sept. 2008.

  2. Q. Zhuge, C. Xue, M. Qiu, J. Hu and E. H.-M. Sha, ``Timing Optimization via Nest-Loop Pipelining Considering Code Size, " Accepted in Journal of Microprocessors and Microsystems, Feb. 2008.

  3. C. Xue, J. Hu, Z. Shao, and E. H.-M. Sha, ``Iterational Retiming with Partitioning: Loop Scheduling with Complete Memory Latency Hiding," Accepted in ACM Transactions on Embedded Computing Systems (ACM TECS), December 2007.

  4. B. Xiao, J. Cao, Z. Shao and E. H.-M. Sha, ``An Efficient Algorithm for Dynamic Shortest Path Tree Update in Network Routing," Accepted in Journal of Communications and Networks, August 2007.

  5. C. Xue, Z. Jia, Z. Shao, M. Wang and E. H.-M. Sha, ``Optimized Address Assignment with Array and Loop Transformations for Minimizing Schedule Length," in IEEE Transactions on Circuits and Systems I (IEEE TCAS), Vol. 55, No. 1, Feb. 2008, pp. 379 - 389.

  6. M. Qiu, E. H.-M. Sha, M. Liu, M. Lin, S. Hua, and L. T. Yang, ``Energy Minimization with Loop Fusion and Multi-Functional-Unit Scheduling for Multidimensional DSP," Accepted in Journal of Parallel and Distributed Computing (JPDC), Nov. 2007

  7. Z. Jia, T. Liu, C Zhang and E. H.-M. Sha, ``Markov Route Decision in Embedded Commnication Middleware," in ACTA Electronica Sinica, Vol. 35, No. 7, July 2007, pp. 1228 - 1233.

  8. K. Chen and E. H.-M. Sha, ``Universal Routing and Performance Assurance for Distributed Networks," in Journal of Interconnection Networks, Vol. 8, No. 1, March 2007, pp. 1 - 28.

  9. B. Xiao, J. Cao, Z. Shao, Q. Zhuge and E. H.-M. Sha, ``Analysis and Algorithms Design for the Partition of Large-Scale Adaptive Mobile Wireless Networks," Accepted in Journal of Computer Communications (JCC), Feb. 2007.

  10. T. Liu, Z. Jia and E. H.-M. Sha, ``Markov FInite Horizon Decision Algorithm of Shortest Path Tree," in Computer Science (CCF Journal), ISDN 1002-137X, Vol 34, No. 8, Sept. 2007, pp. 266 - 270.

  11. C. Xue, Z. Shao, and E. H.-M. Sha, ``Maximizing Parallelism for Nested Loops via Loop Striping," in Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Vol. 47, No. 2, May 2007, pp. 153 - 167.

  12. Z. Shao, M. Wang, Y. Chen, C. Xue, M. Qiu, L. T. Yang and E. H.-M. Sha, ``Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems," in IEEE Transactions on Circuits and Systems (IEEE TCAS), Vol. 54, No. 5, May 2007, pp. 445 - 449.

  13. M. Qiu, C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, ``Energy Minimization for Heterogeneous Wireless Sensor Networks," in Journal of Embedded Computing (JEC), No. 3, 2007.

  14. M. Qiu, Z. Jia, C. Xue, Z. Shao and E. H.-M. Sha, ``Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiprocessor DSP," in The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Vol. 46, No. 1, Jan. 2007, pp. 55-73.

  15. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, ``Optimizing Nested Loops with Iterational and Instructional Retiming," Accepted in Journal of Embedded Computing (JEC), May 2006.

  16. C. Chantrapornchai, W. Surakumpolthorn, and E. H.-M. Sha, ``Design Exploration with Imprecise Latency and Register Constraints," in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol 25, No. 12, Dec. 2006, pp. 2650 - 2662.

  17. T. O'Neil and E. H.-M. Sha, ``Time-Constrained Loop Scheduling with Minimal Resources," in Journal of Embedded Computing (JEC), Vol. 2, No. 1, October 2006, pp. 103 - 117.

  18. C. Xue, Z. Shao, Q. Zhuge, B. Xiao, M. Liu, and E. H.-M. Sha, ``Optimizing Address Assignment for Scheduling DSPs with Multiple Functional Units," in IEEE Transactions on Circuits and Systems (IEEE TCAS), Vol. 53, No. 9, September 2006, pp. 976 - 980.

  19. Z. Shao, J. Cao, K. Chen, C. Xue, and E. H.-M. Sha, ``Hardware/software Optimization for Array & Pointer Bound Checking Against Buffer Overflow Attacks," in Journal of Parallel Distributed Computing (JPDC), Vol. 66, No. 9, September 2006, pp. 1129 - 1136.

  20. Q. Zhuge, C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, ``Design Optimization and Space Minimization Considering Timing and Code Size via Retiming and Unfolding," in Journal of Microprocessors and Microsystems, Vol. 30, Issue 4, June 2006, pp. 173-183.

  21. Z. Shao, Q. Zhuge, M. Liu, C. Xue, E. H.-M. Sha and B. Xiao, ``Algorithms and Analysis of Scheduling for Loops with Minimum Switching," in International Journal of Computational Science and Engineering (IJCSE), Vol. 2, May 2006, pp. 88-97.

  22. K. Chen and E. H.-M. Sha, ``The Fat-Stack and Universal Routing in Interconnection Networks," in Journal of Parallel and Distributed Computing (JPDC), Vol. 66, No. 5, May 2006, pp. 705-715.

  23. Z. Shao, C. Xue, Q. Zhuge, M. Qiu, B. Xiao and E. H.-M. Sha, ``Security Protection and Checking for Embedded System Integration Against Buffer Overflow Attacks via Hardware/Software," in IEEE Transactions on Computers (IEEE TC), Vol. 55, No. 4, April 2006, pp. 443 - 453.

  24. Z. Shao, C. Xue, Q. Zhuge, B. Xiao and E. H.-M. Sha, ``Loop Scheduling with Timing and Switching-Activity Minimization for VLIW DSP," in ACM Transactions on Design Automation of Electronic Systems (ACM TDAES), Vol. 11, No. 1, Jan. 2006, pp. 165 - 185.

  25. Z. Shao, Q. Zhuge, C. Xue and E. H.-M. Sha, ``Efficient Assignment and Scheduling for Heterogeneous DSP Systems," in IEEE Transaction on Parallel and Distributed Systems (IEEE TPDS), Vol. 16, No. 6, June 2005, pp. 516-525.

  26. T. W. O'Neil, and E. H.-M. Sha, ``Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation," in Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Vol. 39, March 2005, pp. 273-293.

  27. Z. Shao, Q. Zhuge, Y. Zhang and E. H.-M. Sha, ``Efficient Scheduling for Low-Power High-Performance DSP Applications," in International Journal of High Performance Computing and Networking (IJHCN), Vol. 1, 2005, pp. 4-16.

  28. Y. Jiang, A. Al-Sheraidah, Y. Wang, E. H.-M. Sha and J. Chung, ``A Novel Multiplexer-Based Low-Power Full Adder," in IEEE Transactions on Circuits and Systems II (IEEE TCAS), Vol. 51, No. 7, July 2004, pp. 345-348.

  29. B. Xiao, Q. Zhuge and E. H.-M. Sha, ``Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking," in ISCA International Journal of Computers and Their Applications, Vol. 11, No. 1, March 2004, pp. 60-75.

  30. D. Surma, E. H.-M. Sha and N. Passos, ``Communication Scheduling with Re-routing based on Static and Hybrid Techniques," in Journal of Circuits, Systems and Computers, Vol. 13, No. 5, Oct. 2004, pp. 1039-1064.

  31. Q. Zhuge, B. Xiao, E. H.-M. Sha, and C. Chantrapornchai, ``Efficient Variable Partitioning and Scheduling for DSP Processors with Multiple Memory Modules," in IEEE Transactions on Signal Processing (IEEE TSP), Vol. 52, No. 4, April 2004, pp. 1090-1099.

  32. Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Code Size Reduction Technique and Implementation for Software-Pipelined DSP Applications," in ACM Transactions on Embedded Computing Systems (ACM TECS), Vol. 2, No. 4, Nov. 2003, pp. 590-613.

  33. E. H.-M. Sha, T. W. O'Neil and N. Passos, ``Efficient Polynomial-time Nested Loop Fusion with Full Parallelism," in International Journal of Computers and Their Applications, Vol. 10, No. 1, March 2003, pp 9-24.

  34. Z. Wang, E. H.-M. Sha and Y. Wang, ``Partitioning and Scheduling DSP applications with Maximal Memory Access Hiding," in Eurasip Journal on Applied Signal Processing (EJASP), No. 9, September 2002, pp. 926-935.

  35. X. Hu, T. Zhou and E. H.-M. Sha, ``Estimating Probabilistic Timing Performance for Real-time Embedded systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), Vol. 9, Number 6, Dec. 2001, pp. 833-844.

  36. T. W. O'Neil, and E. H.-M. Sha, ``Retiming Synchronous Data-Flow Graphs to Minimize Execution Time." in IEEE Transactions on Signal Processing (IEEE TSP), Vol. 49, Number 10, October 2001, pp. 2397-2407.

  37. Z. Wang, T. W. O'Neil and E. H.-M. Sha, ``Optimal Loop Scheduling for Hiding Memory Latency Based on Two Level Partitioning and Prefetching," in IEEE Transactions on Signal Processing (IEEE TSP), Vol. 49, Number 11, November 2001, pp. 2853-2864.

  38. Z. Wang, T. W. O'Neil and E. H.-M. Sha, ``Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching," in Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Vol. 27, Jan. 2001, pp. 215-233.

  39. C. Chantrapornchai, E. H.-M. Sha, and X. S. Hu, ``Efficient Module Selections for Finding Highly Acceptable Designs based on Inclusion Scheduling," in Journal of Systems Architecture (JSA), Vol. 46, No. 11, 2000, pp. 1047-1071.

  40. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Communication Reduction in Multiple Multicasts based on Hybrid Static-Dynamic Scheduling," in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), Vol. 11, No. 9, Sept. 2000, pp. 865-878.

  41. C. Chantrapornchai, E. H.-M. Sha, and X. S. Hu, ``Efficient Acceptable Design Exploration Based on Module Utility Selection," in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol 19, No. 1, Jan. 2000, pp. 19-29.

  42. F. Chen, T. W. O'Neil, and E. H.-M. Sha, ``Optimizing Overall Loop Schedules using Prefetching and Partitioning,'' in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), Vol. 11, No. 6, June 2000, pp. 604-614.

  43. S. Tongsima, E. H.-M. Sha, C. Chantrapornchai, D. Surma and N. Passos, ``Probabilistic Loop Scheduling for Applications with Uncertain Execution Time," in IEEE Transactions on Computers (IEEE TC), Vol. 49, No. 1, Jan. 2000, pp. 65-80.

  44. S. Tongsima, T. W. O'Neil, C. Chantrapornchai and E. H.-M. Sha, ``Properties and Algorithms for Unfolding of Probabilistic Data-flow Graphs," in Journal of VLSI Signal Processing (JVLSI), Vol. 25, No. 3, July 2000, pp. 215-234.

  45. E. H.-M. Sha, and C. Chantrapornchai, ``Optimizing Page Replacement for Multiple-Level Memory Hierarchy," (regular paper) in International Journal of Computers and Their Applications, Vol. 6, No. 4, Dec. 1999, pp. 212-222.

  46. N. Passos and E. H.-M. Sha, ``Scheduling of Uniform Multi-Dimensional Systems under Resource Constraints," (regular paper) in IEEE Transactions on VLSI Systems (IEEE TVLSI), Vol. 6, No. 4, December 1998, pp. 719-730.

  47. S. Tongsima, E. H.-M. Sha, C. Chantrapornchai, and N. Passos, ``Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," (regular paper) in IASTED International Journal of Parallel and Distributed Systems and Networks, Vol. 1, No 4, 1998, pp. 204-211.

  48. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos, ``Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling," (regular paper) in Journal of VLSI Signal Processing (JVLSI), Vol. 18, 1998, pp. 111-123.

  49. D. R. Surma and E. H.-M. Sha, ``Collision Graph based Communication Scheduling for Parallel Systems," (regular paper) in International Journal of Computers and Their Applications (IJCTA). Vol. 5, No. 1, March 1998, pp. 11-22.

  50. L.-F. Chao and E. H.-M. Sha, ``Scheduling Data-Flow Graphs via Retiming and Unfolding," (regular paper) in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), Vol. 8, No. 12, December 1997, pp. 1259-1267.

  51. Q. Wang, E. H.-M. Sha and N. Passos, ``Minimization of Memory Access Overhead for Multi-dimensional DSP Applications via Multi-level Partitioning and Scheduling," (regular paper) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (IEEE TCAS), Vol. 44, No. 9, September 1997, pp. 741-753.

  52. S. Tongsima, E. H.-M. Sha and N. Passos, ``Communication Sensitive Loop Scheduling for DSP Applications," (regular paper) in IEEE Transactions on Signal Processing (IEEE TSP), Vol. 45, No. 5, May 1997, pp. 1309-1322.

  53. L.-F. Chao, E. H.-M. Sha and A. LaPaugh, `` Rotation Scheduling: A Loop Pipelining Algorithm,'' (regular paper) in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 16, No. 3, March 1997, pp. 229-239.

  54. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization," (regular paper) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 16, No. 2, February 1997, pp. 146-159.

  55. Q. Wang, E. H.-M. Sha and N. Passos, ``Optimal Data Scheduling for Uniform Multi-dimensional Applications," IEEE Transactions on Computers (IEEE TC), Vol. 45, No. 12, December 1996, pp. 1439-1444.

  56. N. Passos and E. H.-M. Sha, ``Achieving Full Parallelism using Multi-Dimensional Retiming," (regular paper) in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), Vol. 7, No. 11, November 1996, pp. 1150-1163.

  57. M. Sheliga and E. H.-M. Sha, ``Hardware/Software Co-design With the HMS Framework," (regular paper) in Journal of VLSI Signal Processing Systems (JVLSI), Vol. 13, No. 1, August 1996, pp. 37-56.

  58. N. Passos and E. H.-M. Sha, ``Synchronous Circuit Optimization via Multi-Dimensional Retiming," (regular paper) in IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing (IEEE TCAS), Vol. 43, No. 7, July 1996, pp. 507-519.

  59. N. Passos, E. H.-M. Sha and S. C. Bass, ``Optimizing DSP Flow Graphs via Schedule-Based Multi-Dimensional Retiming," IEEE Transactions on Signal Processing, Vol. 44, No. 1, January, 1996, pp. 150-156.

  60. L.-F. Chao and E. H.-M. Sha, ``Static Scheduling for Synthesis of DSP Algorithms on Various Models," (regular paper) in Journal of VLSI Signal Processing (JVLSI), Vol 10, 1995, pp 207-223.

  61. E. H.-M. Sha and K. Steiglitz, ``Maintaining Bipartite Matchings in the Presence of Failures,'' (regular paper) in Networks Journal, Vol. 23, No. 5, August 1993, pp. 459-471.

  62. E. H.-M. Sha and K. Steiglitz, ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,'' (regular paper) in IEEE Transactions on Computers (IEEE TC), Vol. 42, No. 7, July 1993, pp. 854-862.

  63. E. H.-M. Sha and K. Steiglitz, ``Error Detection in Arrays via Dependency Graphs,'' (regular paper) in Journal of VLSI Signal Processing (JVLSI), Vol. 4, No. 4, October 1992, pp 331-342.

    Submitted Journal Papers Waiting for Review Decision

  64. Q. Xu, J. Xue, J. Hu and E. H.-M. Sha, ``Optimizing Scheduling and Inter-Cluster Connection for Application-Specific DSP Processors," submitted to IEEE Transactions on Digital Signal Processing.

  65. K. Chen, E. H.-M. Sha, and S. Q. Zheng, ``Fast and Noniterative Scheduling in Input-Queued Switches: Algorithm and Hardware", submitted to Journal of Parallel and Distributed COmputing (JPDC).

  66. K. Chen, E. H.-M. Sha, and S. Q. Zheng, ``Providing QoS in Switch Architectures with Fast Noniterative Schedulers," submitted to International Journal of Communication Systems.

  67. C. Xue, Q. Zhuge, Z. Shao, M. Qiu and E. H.-M. Sha, ``Maximize Parallelism for Nested Loops with Iterational and Instructional Retiming," submitted to IEEE Transactions on Parallel and Distributed Systems.

  68. M. Qiu, Z. Shao, Q. Zhuge, C. Xue, M. Liu, and E. H.-M. Sha, ``Minimum-Cost Assignment Considering Timing Probability for Heterogeneous DSP Systems, " submitted to IEEE Transactions on Computers.

  69. M. Liu, Q. Zhuge, Z. Shao, C. Xue and E. H.-M. Sha, `` General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size," submitted to IEEE Transactions on Computers.

  70. M. Liu, Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Efficient Loop Fusion for Two-level Loops Considering Timing and Code Size," submitted to Journal of Embedded Computing.

  71. Z. Wang and E. H.-M. Sha, ``Multiple Loop Nests Scheduling by Integrating Loop Partitioning and Data Padding," submitted to ACM Transactions in Embedded Computing Systems.

  72. T. W. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Extended Retiming: Transforming Data-Flow Graphs to Minimize Clock Period," submitted to International Journal of Computers and Their Applications.



    Refereed Conference Papers

  73. M. Qiu, J. Wu, J. Hu, Y. He and E. H.-M. Sha, ``Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment," in Proc. The 2008 IEEE International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 2008.

  74. M. Qiu, J. Wu, C. Xue, J. Hu, W. Tseng, and E. H.-M. Sha, ``QoS for Networked Heterogeneous Real-Time Embedded Systems," in Proc. ISCA 21st International Conference on Parallel and Distributed Computing and Communication Systems (ISCA PDCCS), New Orleans, Lousiana, Sept. 2008.

  75. M. Qiu, J. Wu, C. Xue, J. Hu, W. Tseng, and E. H.-M. Sha, ``Loop Scheduling and Assignment to Minimize Energy while Hiding Latency for Heterogeneous Multi-Bank Memory," in Proc. IEEE International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, Sept. 2008.

  76. J. Xue, H. Zhao, G. Xing, Z. Shao and E. H.-M. Sha, ``Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems," in Proc. The 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2008), Kaohsiung, Taiwan, August, 2008.

  77. J. Xue, T. Liu, Z. Shao, J. Hu, Z. Jia, E. H.-M. Sha, ``Address Assignment Sensitive Variable Partitioning and Scheduling for DSPs with Multiple Memory Banks," in Proc. The 33rd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 08), Las Vegas, USA, April, 2008, pp. 1453-1456.

  78. J. Xue, E. H.-M. Sha, Z. Shao and M. Qiu, ``Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints," in Proc. The 11th IEEE/ACM DATE Conference: Design, Automation and Test in Europe (DATE), Munich, Germany, March 2008, pp. 1202 - 1207.

  79. M. Qiu, J. Hu and E. H.-M. Sha, ``Adaptive Online Energy Saving for Heterogeneous Sensor Networks," in Proc. The 19th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Cambridge, Massachusetts, Nov. 2007, pp. 294-299.

  80. C. Xue, Z. Shao, M. Liu, Q. Zhuge and E. H.-M. Sha, ``Parallel Network Intrusion Detection on Reconfigurable Platforms," in Proc. The 2007 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2007), Taipei, Taiwan, Dec. 2007, pp. 75-86.

  81. L. Su, K. Zhang and E. H.-M. Sha, ``Applying Situation Awareness to Mobile Proactive Information Delivery," in Proc. The 3rd International Workshop on RFID and Ubiquitous Sensor Networks (USN 2007), In conjunction with the IFIP EUC 2007, Taipei, Taiwan, Dec. 2007, pp. 592-603.

  82. M. Qiu and E. H.-M. Sha ``Energy-Aware Online Algorithm to Satisfy Sampling Rates with Guaranteed Probability for Sensor Applications," in Proc. International Conference on High Performance Computing and Communications (HPCC 2007), Houston, Texas, Sept., 2007, LNCS, pp. 156-167.

  83. M. Wang, Z. Shao, C. Xue and E. H.-M. Sha, ``Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors," in Proc. 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), Daegu, Korea, Aug. 2007, pp. 12-19.

  84. M. Qiu, Z. Shao, C. Xue and E. H.-M. Sha, ``Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems," in Proc. The 10th IEEE International Conference on Design, Automation and Test in Europe (DATE), Nice, France, April 2007, 6 two-column pages, CD Proceedings.

  85. M. Qiu, Z. Jia, Z. Shao, C. Xue, Y. Liu and E. H.-M. Sha, ``Loop Scheduling to Minimize Cost with Data Mining and Prefetching for Heterogeneous DSP," in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Dallas, Texas, Nov. 2006, pp. 572 - 577.

  86. K. Chen, S.Q. Zheng, E. H.-M. Sha, ``QoS Guarantee in Input-Queued Switches with Noniterative Schedulers," in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Dallas, Texas, Nov. 2006, pp. 190 - 195.

  87. M. Liu, C. Xue, M. Qiu and E. H.-M. Sha, ``Optimizing Timing and Code Size Using Maximum Direct Loop Fusion," in Proc. The 19th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2006), San Francisco, CA, Sept. 2006, pp. 126 - 131.

  88. M. Qiu, C. Xue, Q. Zhuge, Z. Shao, M. Liu and E. H.-M. Sha, `` Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability," in Proc. IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Steamboat Springs, Colorado, Sept. 2006, pp. 178 - 181.

  89. M. Qiu, C. Xue, Z. Shao, Q. Zhuge, M. Liu and E. H.-M. Sha, `` Efficient Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network," Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), Seoul, Korea, August, 2006, pp. 25 - 34.

  90. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, `` Loop Striping: Maximizing Parallelism for Nested Loops," Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), Seoul, Korea, August, 2006, pp. 405 - 414.

  91. M. Sheliga, E. H.-M. Sha and N. Passos, ``Reducing Inter Iteration Dependency Delays in Multiprocessor Systems for Large Graphs," in Proc. The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications (CITSA 2006), Orlando, Florida, USA, July 2006, 6 pages, CD Proceedings, Received the Best Paper Award.

  92. M. Qiu, Z. Shao, Q. Zhuge, C. Xue, M. Liu and E. H.-M. Sha, ``Efficient Assignment with Guaranteed Probability for Heterogeneous Parallel DSP," in Proc. The 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2006), Minneapolis, MN, July 2006, pp. 623 - 630.

  93. C. Xue, Z. Shao, M. Liu, M. Qiu, E. H.-M. Sha, ``Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture," in Proc. The 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2006), Minneapolis, MN, July 2006, pp. 375-382.

  94. K. Chen, E. H.-M. Sha and S. Q. Zheng, `` A Fast Non Iterative Scheduler for Input-Queued Switches with Unbuffered Crossbars," in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005, pp 230-235.

  95. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, `` Maximum Loop Distribution and Fusion for Two-Level Loops Considering Code Size," in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005, pp. 126-131.

  96. M. Qiu, M. Liu, C. Xue, Z. Shao, Q. Zhuge and E. H.-M. Sha, `` Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems," in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005, pp. 295-300.

  97. T. W. O'Neil and E. H.-M. Sha, ``Static Scheduling of Split-Node Data Flow Graphs," in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005, pp. 125-130.

  98. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, ``Loop Distribution and Fusion Considering Timing and Code Size for Embedded DSP," in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05), Nagasaki, Japan, Dec. 2005, pp. 121-130.

  99. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, ``Optimizing Nested Loops with Iterational and Instructional Retiming," in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05), Nagasaki, Japan, Dec. 2005, pp. 164-173.

  100. C. Xue, Z. Shao, M. Liu, and E. H.-M. Sha, ``Iterational Retiming: Maximize Iteration-Level Parallelism for Nested Loops," in Proc. The 2005 ACM/IEEE/IFIP International Conference on Hardware - Software Codesign and System Synthesis (ISSS-CODES'05), New York, New York, Sept. 2005, pp. 309-314.

  101. K. Chen, M. Liiu, E. H.-M. Sha, ``A Feasible Baseline Architecture for Building and Evaluating Distributed Systems," in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, NV, Sept. 2005, pp. 348-353.

  102. M. Liu, Z. Shao, C. Xue, K. Chen, E. H.-M. Sha, ``Multi-level Loop Fusion with Minimal Code Size," in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, NV, Sept. 2005, pp. 185-190.

  103. B. Xiao, W. Chen, Y He and E. H.-M. Sha, ``An Active Detecting Method Against SYN Flooding Attack," in Proc. The 11th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2005), Fukuoka, Japan, July 2005, pp. 709-715.

  104. Y. Chen, Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems," in Proc. The IEEE/IFIP International Workshop on Parallel and Distributed EMbedded Systems (PDES 2005), in conjunction with ICAPDS 2005, Fukuoka, Japan, July 2005, pp. 2-6, The best paper award.

  105. K. Chen, B. Xiao and E. H.-M. Sha, ``Universal Routing in Distributed Networks," in Proc. The International Workshop on Distributed, Parallel and Network Applications (DPNA 2005), in conjunction with ICAPDS 2005, Fukuoka, Japan, July 2005, pp. 555-559.

  106. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, ``Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software" in Proc. IEEE International Conference on Information Technology (ITCC 05), Las Vegas, NV, April 2005, pp. 780-785.

  107. C. Xue, Z. Shao, Y. Chen and E. H.-M. Sha, ``Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation," in Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, Philadelphia, PA, March 2005, Vol. 5, pp. 85-88. (Winner of the Best Student Paper).

  108. Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``High-level Synthesis for DSP Applications using Heterogeneous Functional Units," in Proc. IEEE Asia and South Pacific Design Automation Conference (ASP DAC 05), Shanghai, China, Jan. 2005, pp. 302-304.

  109. T. O'Neil and E. H.-M. Sha, ``Using Unfolding to Minimize Inter-Iteration Dependencies", in Proc. IASTED 16th Int. Conf. Parallel and Distributed Computing and Systems (PDCS 04), Cambridge MA, November 2004, pp. 342-347. (Nominee for best paper.)

  110. Z. Shao, Q. Zhuge, B. Xiao and E. H.-M. Sha, `` Switching-Activity Minimization on Instruction-level Loop Scheduling for VLIW DSP Applications," in Proc. IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 04), Galveston, Texas, September, 2004, pp. 224-234.

  111. M. Liu, Q. Zhuge, Z. Shao and E. H.-M. Sha, `` General Loop Fusion Technique for Nested Loops Considering Timing and Code Size," in Proc. ACM/IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Washington DC, September 2004, pp. 190-201.

  112. B. Xiao, J. Cao, Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Shortest Path Tree Update for Multiple Link State Decrements," in Proc. IEEE Global Telecommunications Conference (Globecom), Dallas, Texas, November, 2004, CD Proceedings.

  113. M. Liu, Q. Zhuge, Z.. Shao, K. Chen and E. H.-M. Sha, ``Loop Fusion via Retiming for DSP Applications," in Proc. 17th International Conference on Parallel and Distributed Computing Systems (PDCS), San Francisco , California, September, 2004, pp. 403 - 408.

  114. K. Chen and E. H.-M. Sha, ``The Fat-Stack and Universal Routing in Interconnection Networks," in Proc. 17th International Conference on Parallel and Distributed Computing Systems (PDCS), San Francisco , California, September, 2004, pp. 321 - 326.

  115. Q. Zhuge, Z. Shao, and E. H.-M. Sha, ``Timing Optimization of Nested Loops Considering Code Size for DSP Applications," in Proc. International Conference on Parallel Processing (ICPP), Montreal, Canada, August, 2004, pp. 475-482.

  116. C. Chantrapornchai, W. Surakumpolthorn, and E. H.-M. Sha, ``Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints," in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC), Lecture Note in Computer Science, Springer, Aizu-Wakamatsu City, Japan, August, 2004, pp. 259-270.

  117. X. Chun, Z. Shao, E. H.-M. Sha and B. Xiao, ``Optimizing Address Assignment for Scheduling Embedded DSPs," in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC), Lecture Note in Computer Science, Springer, Aizu-Wakamatsu City, Japan, August, 2004, pp. 64-73.

  118. Z. Shao, Q. Zhuge, M. Liu, E. H.-M. Sha and B. Xiao, ``Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-functional-unit Architectures," in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC), Lecture Note in Computer Science, Springer, Aizu-Wakamatsu City, Japan, August, 2004, pp. 53 - 63.

  119. B. Xiao, J. Cao and E. H.-M. Sha, ``Maintaining Comprehensive Resource Availability in P2P Networks," in Proc. IEEE The Third International Conference on Grid and Cooperative Computing (GCC 2004), Wuhan, China, October, 2004.

  120. B. Xiao, J. Cao, Q. Zhuge, Z. Shao, and E. H.-M. Sha, ``Dynamic Update of SPT in OSPF," in Proc. 2004 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2004), Hong Kong, May, 2004, pp. 18-23.

  121. B. Xiao, J. Cao, Q. Zhuge, Y. He and E. H.-M. Sha, ``Approximation Algorithms Design for Disk Partial Covering Problem," in Proc. 2004 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2004), Hong Kong, May, 2004, pp. 104-109.

  122. Z. Shao, Q. Zhuge, Y. He, C. Xue, M. Liu, and E. H.-M. Sha, ``Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units," in Proc. IEEE International Parallel and Distributed Processing Symposium (IPDPS), (Regular paper) Santa Fe, New Mexico, April, 2004, pp. 891-900.

  123. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, ``Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks," in Proc. IEEE International Conference on Information Technology, (ITCC) , Information Assurance and Security Track, Las Vegas, Nevada, April, 2004, Vol. 1, pp. 409-413.

  124. Z. Shao, Q. Zhuge, Y. He and E. H.-M. Sha, ``Defending Embedded Systems Against Buffer Overflow via Hardware/Software," in Proc. IEEE 19th Annual Computer Security Applications Conference (ACSAC), Las Vegas, Nevada, Dec. 2003, pp. 352-361.

  125. Y. He, Z. Shao, B. Xiao, Q. Zhuge and E. Sha, ``Reliability Driven Task Scheduling for Tightly Coupled Heterogeneous Systems," in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Marina Del Ray, CA, Nov. 2003, pp. 465-470.

  126. B. Xiao, Q. Zhuge, Y. He, Z. Shao and E. Sha, ``Algorithms for Disk Covering Problems with the Most Points," in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Marina Del Ray, CA, Nov. 2003, pp. 541-546.

  127. Z. Shao, Q. Zhuge, Y. Zhang and E. H.-M. Sha, ``Efficient Scheduling for Low-Power High-Performance DSP Applications," in Proc. The 2nd Workshop on Hardware/Software Support for High Performance Scientific and Engineering Computing in conjunction with PACT 2003, New Orleans, Louisiana, Sept. 2003, pp. 135-149.

  128. Q. Zhuge, Z. Shao, B. Xiao and E. H.-M. Sha, ``Design Space Minimization with Timing and Code Size Optimization for Embedded DSP," in Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2003), Newport Beach, California, Oct. 2003, pp. 144-149. (Nominated for the best paper as one of the final four)

  129. B. Xiao, Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Design and Analysis of Improved Shortest Path Tree Update for Network Routing," in Proc. ISCA 16th International Conference on Parallel and Distributed Computing Systems, Reno, Nevada, August 2003, pp. 82-87.

  130. Q. Xu, E. H.-M. Sha and Y. Zhang, ``Application-Specific Interconnection Network design in Clustered DSP Processors," in Proc. ISCA 16th International Conference on Parallel and Distributed Computing Systems, Reno, Nevada, August 2003, pp. 69-75.

  131. Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``An Integrated Framework of Design Optimization and Space Minimization for DSP Applications," in Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 2003, vol. V, pp. 601-604.

  132. Z. Shao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Loop Scheduling for Minimizing Schedule Length and Switching Activities," in Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 2003, vol. V, pp. 109-112.

  133. Z. Wang, S. Hu and E. H.-M. Sha, ``Register Aware Scheduling for Distributed Cache Clustered Architecture," in Proc. IEEE/ACM 2003 ASP Design Automation Conference, Kitakyusyu, Japan, Jan. 2003.

  134. B. Xiao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Analysis and Algorithms for Partitioning of Large-Scale Adaptive Mobile Networks," in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, Nov. 2002, pp. 308-313.

  135. T. O'Neil and E. H.-M. Sha, ``Unfolding a Split-Node Data-Flow Graph," in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, Nov. 2002, pp. 717-722.

  136. Q. Zhuge, E. H. -M. Sha, C. Chantrapornchai, ``CRED: Code Size Reduction Technique and Implementation for Software-Pipelined Applications," in Proc. IEEE Workshop On Embedded System Codesign (ESCODES'02) in conjunction with The 8th IEEE Real-Time and Embedded Technology and Applications Symposium, San Jose, CA, Sept., 2002, pp. 50-56.

  137. Q. Zhuge, B. Xiao, Z. Shao, E. H.-M. Sha and C. Chantrapornchai, ``Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops," in Proc. ACM International Symposium on System Synthesis (ISSS), Kyoto, Japan, Nov. 2002, pp. 144-149.

  138. B. Xiao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Enhanced Route Maintenance for Dynamic Source Routing in Mobile Ad Hoc Networks," in Proc. ISCA 15th International Conference on Parallel and Distributed Computing Systems (PDCS), Louisville, Kentucky, Sept. 2002, pp. 72-77.

  139. T. O'Neil and E. H.-M. Sha, ``Using Retiming to Minimize Inter-Iteration Dependencies," in Proc. ISCA 15th International Conference on Parallel and Distributed Computing Systems (PDCS), Louisville, Kentucky, Sept. 2002, pp. 482-487.

  140. Q. Zhuge, Z. Shao and E. H.-M. Sha, ``Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications," in Proc. International Conference on Parallel Processing, Vancouver, Canada, August 2002, pp. 613-620.

  141. Z. Shao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, ``Analysis And Algorithms For Scheduling With Minimal Switching Activities," in Proc. IEEE Midwest Symposium on Circuits and Systems, Tulsa Oklahoma, August 2002, MPM2L-214, CD Proceedings.

  142. Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Performance Optimization of Multiple Memory Architectures for DSP," in Proc. IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, May 2002, pp. 469-472.

  143. T. W. O'Neil and E. H.-M. Sha, ``Minimizing Resources in a Repeating Schedule for a Split-Node Data-Flow Graph," in Proc. ACM 12th Great Lakes Symposium on VLSI, New York, New York, April 2002, pp. 136-141.

  144. Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP ," in Porc. Workshop on Parallel and Distributed Computing in Image Processing, Video Processing, and Multimedia (PDIVM'2002) in conjunction with IEEE International Parallel and Distributed Processing Symposium (IPDPS 2002), Fort Lauderdale, Florida, April 2002.

  145. Q. Zhuge, B. Xiao, and E. H.-M. Sha, ``Exploring Variable Partitioning for Dual Data-Memory Bank Processors," in Proc. Third Workshop on Media and Streaming Processors in conjunction with IEEE/ACM 34th International Symposium on Microarchitecture, Austin, Texas, Dec. 2001, pp 45-52.

  146. B. Xiao, Q. Zhuge, and E. H.-M. Sha, ``Minimum Dynamic Update for Shortest Path Tree Construction," in Proc. IEEE 2001 GLOBECOM, San Antonio, Texas, Nov. 2001, Vol. 1, pp. 126-131.

  147. Z. Wang, E. H.-M. Sha and X. Hu, ``Combining Partitioning and Data Padding for Scheduling Multiple Loop Nests," in Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Atlanta, GA, Nov. 2001, pp. 67-75.

  148. Z. Wang, Q. Zhuge and E. H.-M. Sha, ``Scheduling and Partitioning for Multiple Loop Nests," in Proc. 14th ACM/IEEE International Symposium on System Synthesis (ISSS), Montreal, Quebec, Canada, October, 2001, pp. 183-188.

  149. Y. Jiang, Y. Wang and E. H.-M. Sha, ``On Low-Power Array Multipliers," in Proc. 8th International IEEE Conference on Electronics, Circuits, and Systems (ICECS 2001), Malta, Sept. 2001.

  150. Y. Jiang, Y. Wang and E. H.-M. Sha, ``Comprehensive Power Evaluation of CMOS Full Adders," in 9th Int. Symposium on Integrated Circuits, Devices & Systems (ISIC 2001), Singapore, Sept. 2001.

  151. T. O'Neil and E. H.-M. Sha, ``On Retiming Synchronous Data-Flow Graphs," in ISCA 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August, 2001, pp. 103-108.

  152. B. Xiao, Q. Zhuge and E. H.-M. Sha, ``Efficient Update of Shortest Path Routing Algorithms for Network Routing," in ISCA 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August, 2001, pp. 315-320.

  153. Y. Jiang, Y. Wang and E. H.-M. Sha, ``Distributed Scaling Algorithm for FFT Computation Using Fixed Point Arithmetic," in ISCA 14th International Conference on Parallel and Distributed Computing Systems, Richardson, Texas, August, 2001, pp. 490-495.

  154. Y. Jiang, A. Al-Sheaidah, Y. Wang, and E. H.-M. Sha, ``A Set of Novel Multiplexer-based Architectures for Full Adder," in Proc. IEEE/WSES World Multiconference on Circuits, Systems, Communications and Computers, Crete, Greece, July, 2001.

  155. J. Xu, E. H.-M. Sha, ``Implementing Parallelism and Scheduling Data Flow Graphs on Java Virtual Machine," in Proc. IEEE International Conference On Acoustics, Speech, and Signal Processing, Salt Lake City, Utah, May, 2001.

  156. Z. Wang, E. H.-M. Sha and Y. Wang, ``Optimal Partitioning and Balanced Scheduling with the Maximal Overlap of Data Footprints," in Proc. IEEE/ACM 11th Great Lakes Symposium on VLSI, West Lafayette, Indiana, March 2001.

  157. V. Andronache, E. H.-M. Sha, and N. Passos, ``Design and Analysis of Efficient Application-Specific On-Line Page Replacement Techniques for Distributed Memory Systems," in Proc. 12th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, November, 2000, pp. 551-556.

  158. T, O'Neil and E. H.-M. Sha, ``Optimal Graph Transformation using Extended Retiming with Minimal Unfolding," in Proc. 12th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, November, 2000, pp. 128-133.

  159. T, O'Neil, E. H.-M. Sha and S. Tongsima, ``Parallelizing Synchronous Data-Flow Graphs via Retiming," in Proc. the 4th International Conference on Algorithms and Architectures for Parallel Processing, Hong Kong, December, 2000, pp. 252-263.

  160. R. Light, W. Maxfield, B. Reed, N. L. Passos, and E. H.-M. Sha, ``Improving Nested Loops' ILP on a Parallel ASIC Design," in ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August, 2000, pp. 105-110.

  161. T. O'Neil and E. H.-M. Sha, ``Minimizing Inter-Iteration Dependencies for Loop Pipelining," in ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August, 2000, pp. 412-417.

  162. Z. Wang, M. Kirkpatrick, and E. H.-M. Sha, ``Optimal Two Level Partitioning and Loop Scheduling for Hiding Memory Latency for DSP Applications," in Proc. ACM 37th Design Automation Conference, Los Angeles, California, June, 2000, pp. 450-455.

  163. J. Ding, J. C. Furgeson and Edwin H..-M. Sha, ``Application Specific Image Compression for Virtual Conferencing," in Proc. IEEE International Conference on Information Technology: Coding and Computing, Las Vegas, Nevada, March 2000, pp. 48-53.

  164. C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Algorithms for Acceptable Design Exploration," in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000, pp. 139-142.

  165. V. Andronache, E. H.-M. Sha and N. Passos, ``Design and Analysis of Efficient Application-Specific On-line Page Replacement Techniques," in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000, pp. 123-128.

  166. J. Ding, M. Kirkpatrick, and E. H.-M. Sha, ``QoS Measures and Implementations Based on Various Models for Real-time Communications," in Proc. 3rd IEEE Symposium on Application-Specific Systems and Software Engineering Technology, Richardson, Texas, March, 2000, pp 106-110.

  167. C. Chantrapornchai, S. Tongsima and Edwin H.-M. Sha, ``Rapid Prototyping Techniques for Fuzzy Controllers," in Proc. 5th Asian Computing Science Conference, Phuket, Thailand, December 1999, pp. 37-49.

  168. T. W. O'Neil, and Edwin H.-M. Sha, ``Rate-Optimal Graph Transformation Based on Extended Retiming and Unfolding," in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999, pp. 764-769.

  169. Z. Wang, V. Andronache, and Edwin H.-M. Sha , ``Optimal Partitioning under Memory Constraints for Minimizing Average Schedule Length," in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999, pp. 758-763.

  170. F. Chen, and E. H.-M. Sha, ``Loop Scheduling and Partitions for Hiding Memory Latencies," in Proc. IEEE 12th International Symposium on System Synthesis, San Jose, CA, November 1999, pp. 64-70.

  171. T. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Optimal Scheduling of Data-Flow Graphs Using Extended Retiming," in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.

  172. N. L. Passos, R. Light, V. Andronache, E. H.-M. Sha, ``Design of 2-D Filters using a Parallel Processor Architecture," in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.

  173. T. O'Neil, S. Tongsima, and and E. H.-M. Sha, ``Extended Retiming: Optimal Scheduling via a Graph-Theoretical Approach," in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol. 4, pp. 2001-2004.

  174. S. Tongsima, T. O'Neil, and E. H.-M. Sha, ``Unfolding Probabilistic Data-flow Graphs Under Different Timing Models," in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol 4, pp. 1889-1892.

  175. T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``A Probabilistic Performance Metric for Real-Time System Design ," in Proc. 1999 7th International Workshop on Hardware Software Co-Design, Rome, Italy, May 1999, pp. 90-94.

  176. T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``Probabilistic Performance Estimation for Real-time Embedded Systems," in Proc. 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, March, 1999, pp. 83-88.

  177. C. Chantrapornchai, E. H.-M. Sha, and X. S. Hu, ``Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections," in Proc. IEEE 9th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March, 1999, pp. 128-131.

  178. Y. Tian, E. H.-M. Sha, C. Chantrapornchai, and P. M. Kogge, ``Efficient Data Placement and Replacement Algorithms for Multiple-Level Memory Hierarchy," in Proc. 10th International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, October, 1998, pp. 196-201.

  179. F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Optimization with Data Prefetching based on Multi-dimensional Retiming," in Porc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, September, 1998, pp. 129-134.

  180. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Communication Reduction Techniques for Multiple Multicasts based on Collision Graphs," in Porc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, September, 1998, pp. 93-98.

  181. F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Algorithm for Timing and Memory Operation Minimization with Register Constraint,'' in Proc. 1998 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS), Boston, Massachusetts, October, 1998, pp. 579-588.

  182. Andrea Leonardi, Nelson L. Passos, and Edwin H.-M. Sha, ``Nested Loops Optimization for Multiprocessor Architecture Design", in Proc. 1998 Midwest Symposium on Circuit and Systems, Notre Dame, Indiana, August, 1998.

  183. C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Scheduling for Imprecise Timing Based on Fuzzy Theory," in Proc. 1998 Midwest Symposium on Circuit and Systems, Notre Dame, Indiana, August, 1998, pp. 272-275.

  184. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos `` Optimizing Circuits with Confidence Probability using Probabilistic Retiming," in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998.

  185. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Compile-time Priority Assignment and Re-routing for Communication Minimization in Parallel Systems," in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998.

  186. M. Sheliga, T. Yu, F. Chen, and E. H.-M. Sha, ``Graph Transformation for Communication Minimization Using Retiming," in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998.

  187. T. Z. Yu, F. Chen and E. H.-M. Sha, ``Loop Scheduling Algorithms for Power Reduction," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Seattle, Washington, May 1998, Vol. 5, pp. 3073-3076.

  188. C. Chantrapornchai, S. Tongsima, E. H.-M. Sha and S. X. Hu, ``Dealing with Impreciseness in Architectural Synthesis," in Proc. IASTED International Conference on Artificial Intelligence and Soft Computing, Cancun, Mexico, May, 1998.

  189. S. Tongsima, C. Chantrapornchai, and E. H.-M. Sha, ``Probabilistic Loop Scheduling Considering Communication Overhead," in Proc. 4th Workshop on Job Scheduling Strategies for Parallel Processing, with IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.

  190. Y. Tian, E. H.-M. Sha, C. Chantrapornchai and P. M. Kogge, ``Optimizing Data Scheduling on Processor-In-Memory Arrays," in Proc. IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998, pp. 57-61.

  191. D. Surma and E. H.-M. Sha, ``Project-Based approach to teaching Microprocessors and their Applications," in American Society for Engineering Education 1998 Spring Conference, Detroit, Michigan, April, 1998, pp. 216-220.

  192. K. Wang, T. Yu and E. H.-M. Sha, ``RCRS: A Framework for Loop Scheduling with Limited Number of Registers," in Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, February, 1998, pp. 386-391.

  193. D. Surma, E. H.-M. Sha and P. M. Kogge, ``SCORE: An efficient technique to reduce congestion in Parallel Systems," in Proc. 10th ISCA International Conference on Parallel and Distributed Computing Systems, New Orleans, LA, October, 1997, pp. 198-203.

  194. Y. Tian, E. H.-M. Sha, C. Chantrapornchai, and P. M. Kogge, ``Efficient Data Placement for Processor-In-Memory Array Processors," in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997, pp. 79-84.

  195. S. Tongsima, E. H.-M. Sha, C. Chantrapornchai, and N. Passos, ``Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997, pp. 363-368.

  196. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos, ``Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time," in Proc. 1997 International Conference on Parallel Processing, Bloomingdale, Illinois, August 1997, pp. 292-295.

  197. C. Chantrapornchai, M. Sheliga, S. Tongsima and E. H.-M. Sha, ``Rapid System Design Framework for Fuzzy Applications,'' in Proc. IEEE 40th Midwest Symposium on Circuits and Systems, Sacramento, California, August, 1997.

  198. D. Surma and E. H.-M. Sha, ``Efficient Communication Scheduling with Re-routing based on Collision Graphs," in Proc. 1997 Annual International Symposium on High Performance Computing Systems, Winnipeg, Manitoba, Canada, July 10-12, 1997, pp. 483-492.

  199. M. Sheliga, E. H.-M. Sha and P. Kogge, ``Hardware/Software Codesign for Video Compression Using the EXECUBE Processor Array," in Proc. 1997 IEEE National Aerospace and Electronics Conference, Dayton, Ohio, July, 1997.

  200. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, ``Imprecise Task Schedule Optimization," in Proc. the Sixth IEEE International Conference on Fuzzy Systems, Barcelona, Spain, July, 1997, Vol. 3, pp. 1265-1270.

  201. T. Yu, N. Passos, E. H.-M. Sha and R. D.-C. Ju, ``Algorithms and Hardware Support for Branch Anticipation," in Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 163-168.

  202. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos, ``Scheduling with Confidence for Probabilistic Data Flow Graphs," in Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 150-155.

  203. D. Surma and E. H.-M. Sha, `` Hybrid Static-Dynamic Communication Scheduling for Parallel Systems," in Proc. 1997 ACM Symposium on Applied Computing, San Jose, California, February, 1997, pp. 374-379.

  204. S. Tongsima, C, Chantrapornchai, E. H.-M. Sha and N. Passos, ``SHARP: Efficient Loop Scheduling with Data Hazard Reduction on Multiple Pipeline DSP Systems," in Proc. 1996 IEEE Workshop on VLSI Signal Processing, San Francisco, California, November, 1996, pp. 253-262.

  205. P. M. Kogge, S. C. Bass, J. B. Brockman, D. Z. Chen and E. H.-M. Sha, ``Pursuing a Petaflop: Point Designs for 100TF Computers Using PIM Technologies," Sixth International Symposium on Frontiers of Massively Parallel Computations, Annapolis, Maryland, October, 1996.

  206. N. Passos and E. H.-M. Sha, ``VHDL Synthesis of Multi-Dimensional Applications: a New Approach," in Proc. 1996 IEEE International Conference on Computer Designs, Austin, Texas, October, 1996, pp. 530-535.

  207. C. Lang, N. Passos and E. H.-M. Sha, ``Polynomial-time Nested Loop Fusion with Full Parallelism," in Proc. 1996 International Conference on Parallel Processing, August, 1996, Vol 3, pp. 9-16.

  208. D. Surma and E. H.-M. Sha, ``Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems," in Proc. 1996 International Conference on Application-specific Systems, Architectures and Processors, Chicago, Illinois, August, 1996, pp. 240-249.

  209. M. Sheliga and E. H.-M. Sha, ``Hardware/Software Co-design for DSP Applications via the HMS Framework," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 2, pp. 1248-1251.

  210. D. Surma, S. Tongsima and E. H.-M. Sha, ``Optimal Communication Scheduling Based on Collision Graph Model," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 6, pp. 3319-3322.

  211. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, ``Minimization of Fuzzy Systems based on Fuzzy Inference Graph," in Proc. IEEE International Symposium on Circuits and Systems, Atlanta, Georgia, May, 1996, Vol. 4, pp. 651-654.

  212. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, ``Rapid Prototyping for Fuzzy Systems," in Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March, 1996, pp. 234-239.

  213. N. Passos and E. H.-M. Sha, ``A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization," in Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996, pp. 66-71.

  214. M. Sheliga, N. Passos and E. H.-M. Sha, ``Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications," in Proc. 4th IEEE International Workshop on Hardware/Software Co-design, Pittsburgh, Pennsylvania, March, 1996, pp. 18-25.

  215. Q. Wang, N. Passos and E. H.-M. Sha, ``Multi-level Partitioning and Scheduling under Local Memory Constraint," (long paper) in Proc. IEEE Symposium on Parallel and Distributed Processing, San Antonio, Texas, December, 1995, pp. 612-619.

  216. N. Passos and E. H.-M. Sha, ``Push-Up Scheduling: Optimal Polynomial-Time Resource Constrained Scheduling for Multi-Dimensional Applications," in Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, November, 1995, pp. 588-591.

  217. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Fully Parallel Synchronous Circuit Design using Multi-Dimensional Interleaving," in Proc. IEEE International Conference on Computer Design, Austin, Texas, October, 1995, pp 440-445.

  218. N. M. Sabine and E. H.-M. Sha, ``Integrating Selective Fault-Tolerance into Hard Real-Time Multiprocessor Schedules," in Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 89-94.

  219. D. R. Surma and E. H.-M. Sha, ``Application-Specific Communication Scheduling on Parallel Systems," in Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 137-139.

  220. S. Tongsima, N. Passos and E. H.-M. Sha, ``Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping," in Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 97-104.

  221. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Memory-Efficient Fully Parallel Loop Transformation," in Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 182-185.

  222. N. Passos and E. H.-M. Sha, ``Memory/Time Optimization of 2-D Filters," in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3223-3226.

  223. L.-F. Chao and E. H.-M. Sha, ``Rate-Optimal Scheduling for Cycle-Static and Periodic Schedules," in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3231-3234.

  224. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Optimizing Synchronous Systems for Multi-dimensional Applications," in Proc. IEEE European Design and Test Conference, Paris, France, March, 1995, pp 54-58.

  225. H. Zhao, N. M. Sabine and E. H.-M. Sha, ``Improving Self-Timed Pipeline Ring Performance Through The Addition of Buffer Loops," in Proc. IEEE Great Lakes Symposium on VLSI, March, 1995, pp 218-223.

  226. M. Sheliga and E. H.-M. Sha, ``Bus Minimization and Scheduling of Multi-Chip Modules," in Proc. IEEE Great Lakes Symposium on VLSI, Buffalo, New York, March, 1995, pp 40-45.

  227. S. Tongsima, N. Passos and E. H.-M. Sha, ``Communication Sensitive Rotation Scheduling," in Proc. 1994 IEEE International Conference on Computer Design, Cambridge, Massachusetts, October, 1994, pp 150-153.

  228. N. Passos and E. H.-M. Sha, ``Full Parallelism of Uniform Nested Loops by Multi-Dimensional Retiming," in Proc. 1994 International Conference on Parallel Processing, vol. 2, St. Charles, Illinois, August, 1994, pp. 130-133.

  229. N. Passos, E. H.-M. Sha and S. C. Bass, ``Loop Pipelining for Scheduling Multi-dimensional Systems via Rotation," in Proc. IEEE/ACM 1994 Design Automation Conference (nominated for the Best Paper Award, 13 nominated out of 439 papers), San Diego, California, June, 1994, pp. 485-490.

  230. L.-F. Chao and E. H.-M. Sha, `` Retiming and Clock Skew for Synchronous Systems," in Proc. IEEE 1994 International Symposium on Circuits and Systems, London, England, May, 1994, vol. 1, pp. 283-286.

  231. N. Passos, E. H.-M. Sha and S. C. Bass, `` Partitioning and Retiming of Multi-dimensional Systems," in Proc. IEEE 1994 International Symposium on Circuits and Systems, London, England, May, 1994, vol. 4, pp. 227-230.

  232. M. Sheliga and E. H.-M. Sha, ``Global Node Reduction of Linear Systems Using Ratio Analysis," in Proc. IEEE Seventh International Symposium on High-Level Synthesis, Niagara-on-the-Lake, Canada, May, 1994, pp. 140-145.

  233. N. Passos, E. H.-M. Sha and S. C. Bass, ``Schedule-Based Multi-Dimensional Retiming on Data-Flow Graphs," in Proc. 1994 International Parallel Processing Symposium, Cancun, Mexico, April, 1994, pp. 195-199.

  234. L.-F. Chao and E. H.-M. Sha, ``Unified Static Scheduling on Various Models," in Proc. 1993 International Conference on Parallel Processing, St. Charles, Illinois, August, 1993, pp. II 231-235.

  235. L.-F. Chao, A. LaPaugh and E. H.-M. Sha, `` Rotation Scheduling: A Loop Pipelining Algorithm,'' in Proc. 30th ACM/IEEE Design Automation Conference, (nominated for the Best Paper Award), Dallas, Texas, June, 1993, pp. 566-572.

  236. L.-F. Chao and E. H.-M. Sha, ``Efficient Retiming and Unfolding," in Proc. 1993 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Minneapolis, Minnesota, April, 1993, pp. I421-I424.

  237. L.-F. Chao and E. H.-M. Sha, ``Static Scheduling of Uniform Nested Loops," in Proc. 7th International Parallel Processing Symposium, Newport Beach, California, April, 1993, pp.254-258.

  238. K. Steiglitz and E. H.-M. Sha, ``Maintaining Bipartite Matchings in the Presence of Failures,'' in Proc. of 7th International Parallel Processing Symposium, (Long Paper), Newport Beach, California, April, 1993, pp. 57-64.

  239. L.-F. Chao and E. H.-M. Sha, ``Rate-Optimal Static Scheduling for DSP Data-Flow Programs", in Proc. IEEE Third Great Lakes Symposium on VLSI, March 1993, pp 80-84.

  240. L.F. Chao, E. H.-M. Sha and A. LaPaugh, ``Scheduling Cyclic Data-Flow Graphs by Retiming with Resource Constraints," in Proc. ACM/IEEE Sixth International Workshop on High-Level Synthesis, Dana Point, California, November, 1992, pp. 111-134.

  241. L.-F. Chao and E. H.-M. Sha, ``Retiming and Unfolding Data-Flow Graphs," in Proc. 1992 International Conference on Parallel Processing, St. Charles, Illinois, August, 1992, pp. II 33-40.

  242. L.-F. Chao and E. H.-M. Sha, ``Algorithms for Min-Cut Linear Arrangements of Outerplanar graphs" in Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May, 1992, pp. 1851-1854.

  243. K. Steiglitz and E. H.-M. Sha, ``An Error-Detectable Array for All-Substring Comparison," in Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May, 1992, pp. 2941-2944.

  244. L.-F. Chao and E. H.-M. Sha, ``Efficient Distributed Reconfiguration for Binary Trees on Diogenes Model," in Proc. 1992 Int'l Phoenix Conf. on Computers and Communications, Scottsdale, Arizona, April, 1992, pp. 464-471.

  245. K. Steiglitz and E. H.-M. Sha, ``Run-Time Error Detection in Arrays Based on the Data-Dependency Graph," in Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San. Francisco, March, 1992, Vol. 5, pp. 625-628.

  246. L.-F. Chao and E. H.-M. Sha, ``Unfolding and Retiming Data-Flow DSP Programs for RISC Multiprocessor Scheduling," in Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San Francisco, California, March, 1992, Vol. 5, pp. 565-568.

  247. L.-F. Chao and E. H.-M. Sha, ``Optimizing Synchronous Systems via Retiming and Unfolding," in Proc. 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March, 1992.

  248. K. Steiglitz and E. H.-M. Sha, ``Explicit Constructions for Reliable Reconfigurable Array Architectures,'' in Proc. Third IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, December, 1991, pp. 640-647.

  249. E. H.-M. Sha and L.-F. Chao, ``Design for Easily Applying Test Vectors to Improve Delay Fault Coverage,'' in Proc. 1991 IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, November, 1991, pp. 500-503.

  250. L.-F. Chao and E. H.-M. Sha, ``Planar Linear Arrangements for Outerplanar graphs," in Proc. 1991 Second Great Lakes Computer Science Conference, Kalamazoo, Michigan, October, 1991.

  251. K. Steiglitz and E. H.-M. Sha, ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,'' in Proc. 1991 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Toronto, Canada, May 1991, Vol. 2, pp. 1001-1004.

References:
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Hsingmean Sha 2008-09-02