IBM 130nm - Layout Verification and Extraction, DRC, LVS, PEX
1. Design Rule Check (DRC)
First of all, start cadence layout tools using icfb &.
Open your inv layout view for editing. Refer to the beginning of Tutorial 3 on how to open an existing cell view for editing.
Now we are going to check if there are any DRC errors in the layout. The layout DRC rules are summarized by the design rules shown above. If you know what could be wrong in the layout, you can try to fix it/them and verify your modified layout by DRC. If not, let's go on to verification.
1. From Virtuoso menu, select Assura -> run DRC... This brings out a DRC form.
2. Put your Working Library, cell, and view names as this picture
3. For your Rules File, enter:
4. Click Set Switches and choose “BEOL_STACK_620”, “Cell”, “Ext_Latchup” and “GridCheck” (hold the “ctrl” key while selecting).
Click "OK" on DRC form. It takes a while to check all the DRC rules defined in the technology files.
When This window pop up, just wait until it complete.
Click YES to see the result.
Ignore these warnings, just fix all other errors.
After Fixing errors, Close your DRC runs by following this: Assura->Close Run
2. Layout vs. Schematic (LVS)
Layout vs. Schematic will compare your layout view with your schematic view.
Run DRC First, and make sure there is no error. and then
Close your DRC runs by following this: Assura->Close Run
To start LVS,
Assura -> Run LVS.
You will see this window pop up. Put your layout and schematic information as this picture, of course use your design names.
For Extract Rules:
For Compare Rules:
For Switch Names:
Click Set Switches and then choose “NO_SUBC_IN_GRLOGIC” and “resimulate_extracted”
For Binding FIles(s):
and then Click OK
You will see this window pop up, just wait more....
You will see similar pop-up window like this when the job is complete…
Make sure that the results say that the schematic and layout matches. If not, there is some problem in either the layout or schematic. Fix the problems in your layout and/or schematic.
Click OK to enter the LVS Debug Environment.
Go View -> LVS Error Report (Current Cell )
You will see the Error Report. Read it carefully and fix the errors in your schematic or layout. By clicking the node name or wire name, the corresponding part in the layout or schematic will be highlighted in the same color as the name.
If you change layout, you should do DRC again.
Redo LVS until everything matches.
If you plan to go to extraction step,
DON'T CLOSE THIS RUN!!! YOU HAVE TO HAVE LVS RUN TO DO EXTRACTION RUN!!!
otherwise, close LVS run by doing: Assura->Close Run
3. Practices Extraction (PEX)
Make sure you run DRC and LVS FIRST, and NOT close run for LVS.
Go Assura -> Run QRC
You will see this Window, if it complains about missing technology directory put this for Setup Dir:
Output should be Spice
Name is any name you want to name your output netlist file
Go to Extraction tap, setup as followed:
Your Filtering page need to be setup as this picture:
Your Netlisting page need to be setup as this picture:
Your Run Details page need to be setup as this picture:
Run Name should be your cell name and Log File will generate automatically once you put your run name.
and then CLICK OK
QRC run completed successfully:
Once it is completed You will find the output file at your cadence working directory.
Your file will look similar to this:
Before you do the HSPICE simulation, you need to comment out or delete the Diode Cards:
DavD194_1_unmatched avC5 vdd! diodenwsx (AREA=1.900E-13
+ perim=5e-08) pcp=3.75e-17 c=1.9e-16
DavD194_2_unmatched gnd! vdd! diodenwsx AREA=4.6116P
+ perim=1.22e-06 pcp=9.15e-16 c=4.6116e-15
DavD194_3_unmatched avC6 vdd! diodenwsx AREA=3.420E-13
+ perim=9e-08 pcp=6.75e-17 c=3.42e-16
Now, you can use HSPICE to make simulation.
You can work in the current cadence directory or make new hspice directory and then work there by copying this output file.
For people using Specter (Cadence simulation tool)
Specter Model Library Location: