EE7240 Integrated Circuit Engineering
Fall '2000

General Information

• Course number: EE7240
• Call number: 1782
• When and where: MWF 12:40 - 1:30 (CEBA 2172)
• Course homepage: EE7240 Homepage
• Prerequisite: Graduate or senior standing in ECE/ChE/ME or Physics background
• Instructor: J. B. Lee, ECE 225, 388-5621, jblee@ee.lsu.edu
• Office hours: MWF 9:00-10:40 or by appointment

• Overview
• Announcements
• Homeworks and Solutions
• Slide Presentations
• Useful Links

Overview

• EE7240 course syllabus
• EE7240 term paper proposal information
• EE7240 term paper information

Announcements

• Submit your nickname by Aug. 28.
• No class on 8/25/2000 (Friday).
• Get Adobe Acrobat Reader.
• Get Microsoft Powerpoint Viewer.
• Mid Exam I on 10/2/2000 (Monday).
• No class on 10/9/2000 (Monday).
• Makeup class for group 1: 10/13 (EE145) and 10/16 (CEBA 1120) 1:30-2:20 pm.
• Makeup class for group 2: 10/16 3-5 pm (CEBA 1121).
• Mid Exam II on 11/29/2000 (Wednesday).
• Term paper is due on 12/8/2000 (Friday).
• Your scores to date. (Updated on 12/11/00.)

Homeworks and Solutions

Slide Presentations

• Chapter 1.
  • History of Microelectronics
  • How to make VLSI?
• Chapter 3.
  • Equivalent planes and directions
  • Diamond lattice
  • Dislocations
  • Frank-Read source
  • Stacking fault
  • Sequence for conveting sand to silicon wafers
  • Fractional distillation
  • Czochralski (CZ) and float-zone (FZ) methods
  • Ingots to silicon wafers
  • Magnetic Czochralski single crystal growth
• Chapter 4.
  • Clean Room
  • Critical defect sizes
  • Gettering
• Chapter 5.
  • Lithography
  • Light sources
  • Exposure system
  • Optics basics (Fraunhofer diffraction, Fresnel diffraction)
  • Resists
  • E-beam lithography
  • X-ray lithography
  • Synchrotron radiation
• Chapter 6.
  • Gate dielectrics roadmap
  • Si-SiO2 interface
  • Oxidation furnace
  • Measurement
  • Deal-Grove model
• Chapter 7.
  • Channel doping roadmap
  • Dopants
  • Error function
  • Irvin's curve
• Chapter 8.
  • Distribution of ions
  • Si channels and channeling effect
• Chapter 10.
  • Wet etching
  • Dry etching
• Chapter 11.
  • Back-end technology
• Chapter 2.
  • VLSI fabrication process overview

Useful Links

• Course related links
  • Overall
    • Fullman Kinetics Semiconductor Manufacturing Process
    • Georgia Tech Virtual Clean Room Homepage
    • Fabrication steps of an FET and a BJT.
  • Chapter 1. Introduction and Historical Perspective
    • History: First Transistor
    • Elements Periodic Table
  • Chapter 3. Crystal Growth, Wafer Fabrication and Basic Properties of Silicon Wafers
    • Crystal structures
    • Diamond lattice structures
    • Properties of semiconductor materials with unit cells applet
    • Production of high-purity silicon
    • Silicon wafer edge rounding
    • Magnetic Czochralski (MCZ) single crystal growth
  • Chapter 4. Semiconductor manufacturing
    • Clean Room
    • Wafer Cleaning
  • Chapter 5. Lithography
    • Diffraction
    • DNQ Novolac resists (1)
    • DNQ Novolac resists (2)
    • Deep UV resists (1)
    • Deep UV resists (2)
    • F2 excimer laser (157 nm)
    • X-ray radiation
  • Chapter 6. Oxidation
    • Scaling the gate dielectric
  • Chapter 7. Diffusion
    • Diffusion
  • Chapter 8. Ion implantation
    • Ion implantation
    • Ion implanter
  • Chapter 10. Etching
    • What are plasmas?
    • Plasma the 4th state
• Other links
  • Semiconductor Research Corporation (SRC)
  • Semiconductor Subway
  • Semi Web
  • SEMATECH
  • Semiconductor Online
  • Semiconductor Net
  • Semiconductor Supersite Network
  • Links for VLSI and MEMS Fabrication
  • Solid State Technology Magazine
  • VLSI Information Links
  • VLSI Related Courses Links
  • LSU CAMD (Center for Advanced Microstructures and Devices)
  • LSU EE7246 - Integrated Sensors and Actuators Class Homepage
  • Instructor's research activity page
  • Monthly Calendar