Joseph S. Friedman

Research Summary

I am an assistant professor of Electrical & Computer Engineering at The University of Texas at Dallas and director of the NanoSpinCompute Laboratory. My research objective is to invent, design, and analyze novel logical and neuromorphic computing paradigms that exploit nanoscale phenomena to achieve greater capabilities than conventional CMOS architectures. In sharp contrast to other proposals for beyond-CMOS and spintronic computing, the central theme of my research is to ensure that individual switching elements can be cascaded and integrated in efficient large-scale computing systems.

from Nature Communications 8, 15635 under CC BY 4.0
All-Carbon Spin Logic
In all-carbon spin logic (ACSL), graphene nanoribbons (GNRs) function as spin-diodes connected by carbon nanotubes (CNTs) in accordance with spin-diode logic (SDL). The exceptional properties of low-dimensional carbon, in concert with electromagnetic wave-based signal propagation, provide the potential for Terahertz operation and a 100x improvement in power-delay product.

Magnetic Domain Wall Neuron
The magnetic domain wall neuron emulates the behavior of neurobiological neurons through manipulation of a magnetic domain wall. This is the first artificial neuron that intrinsically provides the leaking, integrating, firing, and lateral inhibition capabilities without any additional devices or circuitry. This structure is used to perform handwritten digit recognition with 94% accuracy.

Complementary Magnetic Tunnel Junction Logic
Complementary MAgnetic Tunnel junction logic (CMAT) is a spintronic logic family enabling the cascading of MTJ gates. With a complementary structure analogous to CMOS, CMAT provides non-volatile logic that enables non-von Neumann architectures.

Spin-Diode Logic
Spin-diode logic (SDL) is a spintronic logic family in which two-terminal volatile magnetoresistive devices can be directly cascaded. This logic family uses the current passing through the spin-diodes as the source of the magnetic field to switch other spin-diodes. Positive and negative magnetoresistance devices can be cascaded in this manner to realize large-scale computing systems.

Four-Gate FET Threshold Logic
Threshold logic permits the efficient computation of complex multi-input functions, but the noise margins of electronic devices limit the input combinations to the resolution of the device. The recently demonstrated four-gate electrostatically formed nanowires (EFNs) are natural candidates for threshold logic, enabling compact threshold logic circuits.

Stochastic Bayesian Inference
Bayesian inference is a powerful approach for integrating independent conflicting information for decision-making and robotics, performed with limited efficiency by general-purpose computers. Excitingly, Bayesian inference can be performed extremely efficiently through stochastic computing with Muller C-elements. This fault-tolerant circuit structure enables naive Bayesian inference with multiple orders of magnitude decrease in AEDP.

Further Works in Progress

Current projects include spin-transfer torque logic with ferromagnetic nanowires, efficient carbon nanotube logic circuits, novel techniques for stateful memristor logic, skyrmion logic, and a spintronic FPGA.