



Joseph S. Friedman
Research Summary
I am an assistant professor of Electrical & Computer Engineering at The University of Texas at Dallas and director of the NanoSpinCompute Laboratory.
My research objective is to invent, design, and analyze novel logical and neuromorphic computing paradigms that exploit nanoscale phenomena to achieve greater capabilities than conventional CMOS architectures.
In sharp contrast to other proposals for beyondCMOS and spintronic computing, the central theme of my research is to ensure that individual switching elements can be cascaded and integrated in efficient largescale computing systems.
from Nature Communications 8, 15635 under CC BY 4.0 
In allcarbon spin logic (ACSL), graphene nanoribbons (GNRs) function as spindiodes connected by carbon nanotubes (CNTs) in accordance with spindiode logic (SDL). The exceptional properties of lowdimensional carbon, in concert with electromagnetic wavebased signal propagation, provide the potential for Terahertz operation and a 100x improvement in powerdelay product. 
The magnetic domain wall neuron emulates the behavior of neurobiological neurons through manipulation of a magnetic domain wall.
This is the first artificial neuron that intrinsically provides the leaking, integrating, firing, and lateral inhibition capabilities without any additional devices or circuitry.
This structure is used to perform handwritten digit recognition with 94% accuracy. 


Complementary MAgnetic Tunnel junction logic (CMAT) is a spintronic logic family enabling the cascading of MTJ gates.
With a complementary structure analogous to CMOS, CMAT provides nonvolatile logic that enables nonvon Neumann architectures. 
Spindiode logic (SDL) is a spintronic logic family in which twoterminal volatile magnetoresistive devices can be directly cascaded.
This logic family uses the current passing through the spindiodes as the source of the magnetic field to switch other spindiodes.
Positive and negative magnetoresistance devices can be cascaded in this manner to realize largescale computing systems. 


Threshold logic permits the efficient computation of complex multiinput functions, but the noise margins of electronic devices limit the input combinations to the resolution of the device.
The recently demonstrated fourgate electrostatically formed nanowires (EFNs) are natural candidates for threshold logic, enabling compact threshold logic circuits. 
Bayesian inference is a powerful approach for integrating independent conflicting information for decisionmaking and robotics, performed with limited efficiency by generalpurpose computers.
Excitingly, Bayesian inference can be performed extremely efficiently through stochastic computing with Muller Celements.
This faulttolerant circuit structure enables naive Bayesian inference with multiple orders of magnitude decrease in AEDP. 

Further Works in Progress
Current projects include spintransfer torque logic with ferromagnetic nanowires, efficient carbon nanotube logic circuits, novel techniques for stateful memristor logic, skyrmion logic, and a spintronic FPGA.
