Joseph S. Friedman


Spin-Diode Logic

Spin-diode logic (SDL) is a spintronic logic family in which two-terminal volatile magnetoresistive devices can be directly cascaded. This logic family uses the current passing through the spin-diodes as the source of the magnetic field to switch other spin-diodes. Positive and negative magnetoresistance devices can be cascaded in this manner to realize large-scale computing systems.

Spin-Diode Logic Family Structure

A "spin-diode" is the spintronic analog of an electrical diode: the application of an external magnetic field greater than the spin-diode threshold BT switches the spin-diode between an insulating state and a conducting state. Numerous phenomena have been demonstrated experimentally to produce this behavior, and the exact nature of the physics is not relevant to the logic structure. Two potential spin-diode magnetoresistance curves are shown below. This SDL family can be applied to various types of magnetoresistance devices, with only minor differences in circuit topology. However, while the logic circuit structure is not significantly affected by the device behavior, the particular physical characteristics of the spin-diodes determine the computing system efficiency.

In SDL, a constant bias voltage is applied to all spin-diodes, and the current through each spin-diode is modulated by magnetic fields created by control wires. One terminal of the spin-diode is always connected to the circuit high voltage, while the other terminal is connected to the low voltage. The currents through the spin-diodes are routed through the control wires of other spin-diodes to create a magnetic field. This magnetic field through a spin-diode activates the magnetoresistance, switching the resistance state of the spin-diode.

Binary logic states are represented by the spin-diode currents as state variables. Large currents resulting from magnetic fields that impose the conductive state are a logical "1", and small currents resulting from magnetic fields that impose the resistive state are a logical "0".

InSb Bilayer Avalanche Spin-Diode Logic

A particularly exciting semiconductor device was recently experimentally demonstrated to exhibit nearly ideal spin-diode behavior (though the logic style initially proposed for its use does not permit cascading). With the application of an external magnetic field greater than BT, this InSb p-n bilayer channel avalanche spin-diode switches from a resistive to a conductive state. In their experiment, BT is tuned through control of a voltage bias applied across the device.

The resistance through the bilayer avalanche spin-diode can be controlled by currents through two control wires. When the control wires are biased in the same direction, the magnetic fields are additive, resulting in OR functionality. When the voltages on the control wires are in opposite directions, the magnetic fields counteract, resulting in an AND gate with an inverted input (referred to here as IAND).

With the OR and IAND basis functions, all Boolean logic operations can be performed. For example, the one-bit half adder below calculates the binary addition of two input bits (A and B) to generate a sum (S) and carry-out (Cout) bit. This circuit computes the half adder function optimized for bilayer avalanche SDL with only five spin-diodes. In general, SDL circuits require fewer than half the number of active devices in CMOS.

InMnAs Heterojunction Spin-Diode Logic

SDL was initially developed for InAs/InMnAs magnetoresistive semiconductor heterojunction diodes. In these devices, magnetic fields in either direction cause an increased resistance, with the current dependent on the voltage bias.

This positive magnetoresistance enables three basis logic gates:
  • Inverter, with one control wire
  • NOR Gate, with two control wires biased in opposite directions
  • XNOR Gate, with two control wires biased in the same direction
As with InSb bilayer avalanche SDL, a wired-OR gate can be formed by simply merging two current lines.

Related Publications

  1. J. S. Friedman, Cascaded All-Carbon Spin Logic based on Graphene Nanoribbon Magnetoresistance, Joint IEEE International Magnetics Conference & Conference on Magnetism and Magnetic Materials, Jan. 2019.
  2. J. S. Friedman, Cascaded Spintronic Logic Gates based on Graphene Nanoribbon Magnetoresistance: All-Carbon Spin Logic, Proc. SPIE Spintronics XI, Aug. 2018 (invited).
  3. J. S. Friedman, A. Girdhar, S. K. Heinrich-Barna, W. A. Chalifoux, J.-P. Leburton, A. V. Sahakian, 2D Carbon for Cascaded Spintronic Logic, International Conference on Superlattices, Nanostructures and Nanodevices, July 2018.
  4. V. Vyas, J. S. Friedman, Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic, Proc. IEEE/ACM International Symposium on Nanoscale Architectures, July 2018.
  5. S. K. Heinrich-Barna, J. P. Leburton, J. S. Friedman, All-Carbon Spin Logic Sensor for RRAM Arrays, Proc. IEEE International Symposium on Circuits & Systems, May 2018 (invited).
  6. J. S. Friedman, A. Girdhar, R. M. Gelfand, G. Memik, H. Mohseni, A. Taflove, B. W. Wessels, J.-P. Leburton, A. V. Sahakian, Cascaded Spintronic Logic with Low-Dimensional Carbon, Nature Communications 8, 15635 (2017).
  7. J. S. Friedman, E. R. Fadel, B. W. Wessels, D. Querlioz, A. V. Sahakian, Bilayer Avalanche Spin-Diode Logic, AIP Advances 5:11, 117102 (2015).
  8. J. S. Friedman, B. W. Wessels, A. V. Sahakian, System and Method for Spin Logic, U.S. Patent #9,186,103 (2015).
  9. M. G. A. Martins, F. S. Marranghello, J. S. Friedman, A. V. Sahakian, R. P. Ribas, A. I. Reis, Enhanced Spin-Diode Synthesis using Logic Sharing, Proc. EUROMICRO Digital System Design Conference, Aug. 2015.
  10. M. G. A. Martins, F. S. Marranghello, J. S. Friedman, A. V. Sahakian, R. P. Ribas, A. I. Reis, Automated Synthesis Approaches for Digital Integrated Design of Spin-Diode Circuits, International Workshop on Logic & Synthesis, June 2015.
  11. J. S. Friedman, B. W. Wessels, D. Querlioz, A. V. Sahakian, High-Performance Computing based on Spin-Diode Logic, Proc. SPIE Spintronics VII, Aug. 2014 (invited).
  12. J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, Logic Cells Based on Spin Diode and Applications of Same, U.S. Patent #8,912,821 (2014).
  13. M. G. A. Martins, F. S. Marranghello, J. S. Friedman, A. V. Sahakian, R. P. Ribas, A. I. Reis, Spin Diode Network Synthesis using Functional Composition, Proc. Symposium on Integrated Circuits and Systems Design, Sep. 2013.
  14. J. S. Friedman, B. W. Wessels, A. V. Sahakian, High-Performance Spintronic Computing with Magnetoresistive Semiconductor Heterojunctions, Proc. SPIE Spintronics VI, Aug. 2013 (invited).
  15. J. S. Friedman, Cascaded Magnetoresistive Spintronics: A Pathway for Computing Beyond 10 GHz, CMOS Emerging Technologies Research Symposium, July 2013 (invited).
  16. J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, A Spin-Diode Logic Family, IEEE Transactions on Nanotechnology 11:5, 1026-1032 (2012).
  17. J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, InMnAs Magnetoresistive Spin-Diode Logic, Proc. ACM Great Lakes Symposium on VLSI, May 2012.