Jie, Damian and Erick got paper into ASBD@ISCA 2015
One of studies that recently we collaborated with Texas Instruments has been accepted from workshop on Architectures and Systems for Big Data held in conjunction with ISCA'15. This paper titled by "A Hardware/Software CoDesign Emulation Platform for SSD-Accelerated Near Data Processing" describes a system to evaluate near-data processing in flash devices by implementing a real hardware prototype on a multi-core system. The prototype appears to be a credible and effective platform for evaluating systems where high-bandwidth storage can be read and processed on its way to the host.
This work will be demonstrated at Portland, Oregon, June.
Gieseo got paper into WARP@ISCA 2015
One of our recent papers, entitled by "NVM-Charade: An Open Sourced FPGA-Based NVM Characterization Scheme" has been accepted by WARP at ISCA'15.
Accurate characterization of real device samples is essential for understanding the true potential of the emerging non-volatile memories (NVMs), and identifying their optimal placement in the memory hierarchy. Unfortunately, most existing publicly-available resources provide performance and reliability data acquired from analytic models or simulation based studies. In this work, we present NVM-Charade, an open-sourced, highly configurable FPGA based empirical data extraction scheme for various NVM technologies. At this juncture, our proposed scheme is a comprehensive evaluation setup with fine-grained user control that extracts reliable endurance, retention, latency, and power data for a real MRAM product.
Read more: [ Program ]
Shuwen is going to Intel
Shuwen is going to join Intel when she finishes her master this semester. During the past 2 years, she attended our research mentoring program and developed a good research topic associated with a novel GPU thread block scheduling as her first base. In addition, she secured several key technologies in emerging non-volatile memory. We believe that this is good for her and good for Intel. We're little sad though as she is good as gold for all of our lab members. Well done, Shuwen, and the best of luck! We'll miss you a lot.
Jie's WiP report has been accepted from FAST 2015
Jie's working-in-process report titled by "Shared Non-Volatile Memory Cache for Energy-Efficient High Throughput GPU Computing" has been accepted from USENIX FAST'15. In this work, we redesign the shared last-level cache (LLC) of a modern GPU device by introducing nonvolatile memory (NVM), which can significantly address the cache thrashing issues with low power consumption. Our results show that our baseline NVM-cache improves the the overall IPC performance of a conventional LLC on diverse memory intensive workloads by 10%, while reducing the power consumption of the underlying DRAM and LLC itself by 36% and 55%, respectively. Further, our 3D-stacked NVM-cache improves such performance by 20% with power consumption similar to the conventional cache.
This work has been demonstrated at San Jose, Feb 16~19 2015.
National Science Foundation (NSF) supports Prof. Jung's Host-Assisted, Software-Defined Solid-State Disk project (Single PI)
Over the past two decades flash-based storage has crept up from a niche and relatively unknown storage technology to the mobile and embedded medium of choice, and made significant in-roads in the laptop and server arenas in the incarnation of Solid State Disk (SSD). Increasingly, many applications use SSDs and trends indicate that SSD usage will grow significantly. However, SSDs are no silver bullet - in reality, the flash firmware in all commercial SSDs is very rigid and highly unadaptable across input/output (I/O) workloads creating sincere challenges which include the added cost of firmware per SSD, firmware inflexibility, and assisting SSD hardware limitations. Prof. Jung's host-assisted, software-defined solid-state disk (HASD) project will address these key issues. The research will investigate how SSDs should achieve the flexibility they need to perform best for a variety of I/O workloads by being software-defined.
Prof. Jung, Wonil, and Shuwen's paper got into Transactions on Storage (2015)
Our paper titled by “NANDFlashSim: High-Fidelity, Micro-Architecture-Aware NAND Flash Memory Simulation” has been accepted from ACM Transactions on Storage. In this paper, we present the first open-source micro-architecture-level simulation tool for NAND flash memory, which implements a detailed timing model and energy model for various NAND flash operations. This work will be appeared in 2015.
Department of Energy (DOE) supports Prof. Jung's non-volatile memory HW/SW codesign project
To explore impacts of diverse non-volatile memory (NVM) technologies in modern computer architecture and systems, it is required to have fast, high fidelitous and accurate NVM simulation/emulation research tools. Unfortunately, modeling NVM technologies for the broad range of variety is non-trivial research area as there are multiple design parameters and unprecedented device-level considerations. Our lab is in a development phase of several NVM research frameworks, including open-source simulation models, FPGA-based NVM emulators, and hardware validation prototypes. In addition to offering these valuable research vehicles, we also propose a hardware-software codesign environment that will allow application, algorithm and system developers to influence the direction of future architectures, thereby satisfying diverse computing area demands. Prof. Jung NVM projects are supported by U.S. Department of Energy and cooperate with National Energy Research Scientific Computing Center.
Prof. Jung's Paper Got into IEEE Transactions on Computers (2015)
Prof. Jung's paper titled by “Exploring Design Challenges in Getting Solid State Drives Closer to CPU” has been accepted from IEEE Transactions on Computers. As a single author of this work, he quantitatively analyzes the design challenges faced by high-performance SSD, and offers diverse architectural characteristics by evaluating state-of-the-art real PCIe/SATA SSD products with his in-house resource analyzer and dynamic evaluation platform. The empirical research includes host-side resource usages (memory, kernel modules, CPU, etc.), dynamic power consumption and energy analysis. This work will be appeared in 2015.
Read more: [ Paper ]
Prof. Jung Joins Program Committee of IEEE IPDPS
Prof. Jung joins computer architecture program committee of IEEE International Parallel & Distributed Processing Symposium (IPDPS). IPDPS is an international forum for engineers and scientists from around the world to present their latest research findings in all aspects of parallel computation. In addition to technical sessions of submitted paper presentations, the meeting offers workshops, tutorials, and commercial presentations & exhibits. IPDPS represents a unique international gathering of computer scientists from around the world.
Read more: [ CFP ]
CAMEL's SSD Paper in ZDNet
Our one of recent works has been discussed in ZDNet, which is one of popular business technology news websites (by Robin Harris) -- "Making flash SSDs look like disks isn't easy. In fact, advanced high-performance SSDs use more power and run much hotter than disks. They aren't your father's thumb drive,"
This article introduces a part of our ongoing series of UT-Dallas research on high performance SSDs, and commends our work for SSD/NVM researchers. The article said "It’s important that we have good data on actual today’s SSD behavior instead of impressions gained years ago with simpler and slower devices. If high-performance SSDs loom large in your planning this paper (UT-Dallas) is well worth a read".
Based on reviewers and researchers' requests, we are preparing other works to reveal the thermal factors and power throttling issues for many different types of SSDs, and one of them is expected to be appeared in a major computer journal.
HIOS Debuts in ISCA 2014
Our host interface I/O scheduling algorithm (named by HIOS) has been demonstrated in The 41st International Symposium on Computer Architecture (ISCA), which is one of top-tier conferences in computer architecture society. This year, we shared two significant challenges (i.e., garbage collection and resource conflict) that most SSD systems face with other researchers and engineers, and proposed a novel scheduling method that redistributes the GC overheads across non-critical I/O requests and reduces channel resource contention.
Read more: [ IEEE paper ]
Two More Architecture/System Papers Got Accepted
This week, CAMEL has published an invited journal paper titled by "Exploring the Future of Out-Of-Core Computing with Compute-Local Non-Volatile Memory" to Scientific Programming. Our collaborative research paper titled by "ZombieNAND:Resurrecting Dead NAND Flash for Improved SSD Longevity" also got accepted from MASCOTS 2014. We are looking forward to meet you in Paris, September 2014!.
CAMEL's Four Architecture/System Papers at Top Venues
We have four architecture papers being presented in big venues, next week. The papers, listed below, will demonstrate what we do for Non-Volatile Memory and GPU at UT-Dallas.
- "Power, Energy and Thermal Considerations in SSD-Based I/O Acceleration," Jie Zhang, Mustafa Shihab, Myoungsoo Jung, USENIX HOTSTORAGE'14
- "HIOS: A Host Interface I/O Scheduler for Solid State Disks," Myoungsoo Jung, Wonil Choi, Shekhar Srikantaiah, Joonhyuk Yoo, Mahmut Kandemir, ISCA'14
- "GPUdrive: Reconsidering Storage Accesses for GPU Acceleration," Mustafa Shihab, Karl Taht, Myoungsoo Jung, ASBD at ISCA'14
- "Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory," Youngbin Jin, Mustafa Shihab, Myoungsoo Jung, MemoryForum ISCA'14
Mustafa and Karl Got Paper into ASBD@ISCA2014
Mustafa and Karl's paper titled by "GPUdrive: Reconsidering Storage Accesses for GPU Acceleration" has been accepted from (Architectures and Systems for Big Data) ASBD @ISCA'14!!
In this preliminary study, we analyze two critical performance bottlenecks in GPU-accelerated data processing and then study design considerations to reduce the overheads imposed by file-driven data movements in GPU computing.
Congratulations, Mustafa and Karl!!
Our STT-MRAM Study Has Been accepted from MemoryForum@ISCA2014
One of our recent studies titled by "Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory" has been accepted from Memory-Forum@ISCA'14!!
In this work he studies diverse device-level parameters of STT-MRAM to make the storage capacity of STT-MRAM comparable to DRAM with better performance as well as power consumption behavior. Under Prof. Jung's supervision, he also presents analytic models to ﬁnely tune the thermal stability factor, which is related to STT-MRAM’s magnetic layer and corresponding transistor, and address the challenges that storage-class STT-MRAM faces in replacing DRAM as a working memory.
Jie Got Paper into HOTSTORAGE 2014
Jie's paper analyzing operating temperature, dynamic power, and energy in state-of-the-art SSDs with high numbers of channels and chips has been accepted in HotStorage'14. This work also brings up some important considerations that storage society needs to pay attention regarding diverse types of modern flash-based SSD.
USENIX HotStorage is one of top venues in memory, storage and file system research area. Congratulations Jie and Mustafa!!. We are looking forward to having discussion on our findings with other architecture and storage researchers in Philadelphia this year!
Prof.Jung Joins Program Committee of IEEE ICCD 2014
Prof. Jung joins computer systems and applications program committee of ICCD. Basically, ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, veriﬁcation and test, design tools and methodologies, circuit design, and technology.
Prof. Jung and Wonil Got Paper into ISCA 2014
Our paper describing a novel host interface I/O scheduler has been accepted in ISCA'14. The proposed scheduler, both GC-aware and QoS-aware, redistributes the GC overheads across non-critical I/O requests and reduces channel resource contention.
we are so exciting to demonstrate our scheduler atop high performance SSD in ISCA, which is one of top-tier conferences in computer architecture society (ISCA, HPCA, ASPLOS, MICRO)!!
Triple-A Debuts in ASPLOS 2014
Our paper proposing a Non-SSD based Autonomic All-Flash Array (Triple-A), which is a self-optimizing, from scratch NAND flash cluster just successfully debuted in ASPLOS'14. We are proud of demonstrating one of our flash array works at ASPLOS, which is one of top-tier conferences in computer architecture society this year!!
Sprinkler Debuts in HPCA 2014
Our novel device-level SSD controller (Sprinkler) has successfully debuted in HPCA, which is one of top-tier conferences in computer architecture society!! Our sprinkler targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, it relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions by over-committing flash memory requests to specific resources.
Prof. Jung Begins Undergraduate Research Mentoring in UT-Dallas
CAMELab just started to mentor undergraduate students in helping computer architecture and engineering research. The main goals of this undergraduate research mentoring program are i) to provide opportunities exploring diverse research topics in architecture, system and operating system, ii) guide how to perform research, iii) to teach how to use academic research tool such as Gem5, GPGPUsim and NANDFlashSim, and iv) to provide a chance connecting with graduate students to get more practice in performing research. As one of mentoring programming example, Prof. Jung and his students have research cleaning seminar for about 4 hours per week. Registered undergraduate students will explore GPU, SSD, multicore, NUMA, NUCA and emerging memory system research topics demonstrated at the top-tire conferences in computer architecture (e.g, ISCA, ASPLOS, MICRO, HPCA), and will perform computer architecture research with Prof. Jung's help.
Our Out-Of-Core Computing with NVM has been nominated as the best paper in SC 2013
Our paper describing a future NVM technology for accelerating scientific applications has been nominated as both a best student paper and best paper in SC'13 (Supercomputing'13)!!!
In this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.
CAMEL Settles Down in Dallas
Prof. Jung and his student from PennState (Wonil Choi, co-advised by Dr. Kandemir) move to UT-Dallas and begin to investigate and explore reliable, robust, safe and intelligent computer and memory architecture including emerging Non-Volatile Memory (NVM) technology, finding novel technologies to offer all these properties for next-generation many-core, graphic processing unit, persistent memory systems, embedded system, high performance computing and solid state disks.