As a Teaching Assistant in the Electrical Engineering department, My duties involves conducting individual laboratory sessions and assist professors in conduction of course work both at undergraduate and graduate level. This is a scholarship with full tuition waiver and stipend provided to me by the University to support my research work leading to a thesis to complete my Masters Degree Program.
As a hardware engineer was responsible for the design and implementation of Amplifier Controller Card, which provides the control functionality to the Optical Booster Amplifier sytem. The Controller Card sets the configuration parameters in the system and reads and displays alarm related parameters in a GUI. This Card incorporates Motorola MC68302 Microprocessor for implementation.
This system was capable of receiving Multi-rate SONET/SDH data and 10/100 mbps Ethernet data as input from the line side and transmits in 32 wavelength DWDM grid defined by ITU-T. This system has a total span of 640 kms in 8 hops and each individual span covering 80 kms in both linear as wells as ring configurations. EDFA based Optical Amplifier serves as repeater in intermediate spans. The system also has provision for Add/Drop of wavelenghts in two of those eight locations. This system was meant for deployment in the back bone telecom network. I was involved in the software and hardware architecture design of the system. As a hardware engineer, I was involved in the design and implementation of Supervisory and Central Controller Card. This card is the central nervous system of the systems which is responsible for system parameter setting and alarm reporting in a GUI. This card supports a 2 mbps supervisory link which is capable of conveying parametric and alarm information and omni orderwire channel to facilitate communication between exchange operators. This card utilized Motorola PowerPC MPC860 Microprocessor for implementation.
This system was targetted towards Metropolitan area and was meant to facilitate the triple play of voice, data and video over telecommunication network and is capable of a maximum bandwidth of 20 gbps. It receives Multirate SDH data from line side along with Fast and Gigabit Ethernet data from the line side, converts this data in to virtually concatenated (VC) containers and then uses a Time Space Time (TST) switch to route the incoming data through any of the wavelength which has unoccupied bandwidth. My task involved the design and implementation of the Central Controller Card of this system, whose functionality was on similar lines compared to DWDM system. I was also involved in the design and implementation of Time Switch and Clock Control Card, which implements the afore mentioned TST switch. In addition to it, it also generates the system clock for all the other modules in the system. This card involved extensive high speed design with LVDS data rate of up to 777.77 Mbps.
Course Work: VLSI Design, Analog Integrated circuit Design, Computer Architecture, Design Automation of VLSI Systems, IC Testing and Testable Design, Analog Integrated System Design, DSP Architectures, Digital Signal Processing and Biomedical Electronics
Completed the program in First Class with Distinction. Stood 4th overall in a class of 56 Students.
Awarded Teaching Assistantship by UTD to pursue Master of Science Program
Award of Merit by C-DOT for outstanding contribution to the project work
Award of Recognition for contribution in successful completion of DWDM System Implementation
Merit Scholarship with tuition waiver awarded by NIT, Allahabad, India to pursue Undergraduate Program
Stood in top 4% of the District in Higher Secondary School Examination
Working Knowledge in Unix, Linux and Windows Platforms
C,C++, VHDL and Verilog
FPGA Design Tools from Xilinx (ISE), Altera(Quartus) and Synopsis
Cadence Viruoso IC design Environment, MATLAB
Software Implementation of Polyphase Coded Pulse Compression Technique Combined with Windowing Technique to boost Signal to Noise Ratio (SNR) Targeted towards deployment in Matched Filters in Receivers of Radar Systems.
Design of Sinusoidal Oscillator using Four Terminal Floating Nullor (FTFN) (Undergraduate Thesis work) in National Hardware Symposium, Anna University, Chennai, India (March 2000)