Selected Publications

• GHz+ Fault Modeling and GHz Test

  • JETTA'02: Fault Modeling and Testing in High-Speed SoCs (PDF)
  • VTS'02: Test Pattern Generation for Signal Integrity Faults (PDF)
  • VTS'01: Built-In-Chip Testing of Voltage Overshoots (Postscript)
  • DAC'00: Modeling and Simulation of Real Defects Using Fuzzy Logic (Postscript)
  • ICM'00: The Effect of Gate Orientation on Fault Detection (Postscript)

• Core Based System Design and Test

  • VTS'02: Testing High-Speed SoCs Using Low-Speed ATEs (PDF)
  • ITC'00: An ILP Formulation to Optimize Test Access Mechanism (Postscript)
  • TODAES-00: Integrated Test of Interacting Controllers and Datapaths (Postscript)
  • TSW'00: Test Access Mechanism for System-on-Chip (Postscript)
  • JETTA-Oct. 99: Embedded Core Testing Using Pipelining (Postscript)
  • DAC'99: Microprocessor Based Testing for SoC's (Postscript)
  • VTS'98: Parallelism in Embedded Core Testing (Postscript)
  • DAC'97: Integrated Controller-Datapath Fault Testing (Postscript)

• Design for Testability

  • DAC'00: Synthesis-for-Testability of RTL Structures (Postscript)
  • DATE'99: Controller Synthesis for Integrated Testing (Postscript)
  • DATE'98: Bypass Scheme for Core Testing (Postscript)
  • EDTC'97: BIST Insertion Using Behavioral Analysis (Postscript)
  • EURO-DAC'92: SYNTEST: A System Level Design for Test (PDF)

• IP Packet Processing Architecture

  • ICC'02: An IP Packet Forwarding Technique Based on Partitioned Lookup Table (PDF)
  • MWSCAS'01: System Requirements for Super Terabit Routing (PDF)

• High Level Synthesis

  • TVLSI'00: Stability-Based Algorithms for High Level Synthesis (Postscript)
  • ISCAS'96: Avoiding False Paths Caused by Resource Binding(Postscript)
  • DAC'93: Redesign in Datapath Synthesis (Postscript)
  • EURODAC'92: Scheduling Using Neural Network (Postscript)
  • DAC'92: Scheduling and Allocation (Postscript)

• Estimation at Register Transfer Level

  • EURODAC'96: Delay Estimation at Register Transfer Level (Postscript)
  • DAC'93: Area Estimation at Register Transfer Level (Postscript)

• Low Power Design Methodologies

  • MWSCAS'00: Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI (PDF)
  • DATE'00: Detecting Controller Faults Using Power Analysis (Postscript)
  • TVLSI-June 99: Power Management Based on Multiple Clocks (Postscript)
  • DAC'96: Low Power Management Scheme (Postscript)

• All Publications

  • List (ASCII)