JOURNAL PUBLICATIONS
--------------------

9. M. Nourani A. Attarha,
   ``Signal Integrity: Fault Modeling and Testing in High-Speed SoCs,''
   Journal of Electronic Testing: Theory and Applications
   (JETTA), pp. 539-554, 2002.

8. M. Nourani A. Attarha,
   ``Detecting Signal Overshoots for Reliability Analysis in High-Speed SoCs,''
   IEEE Transactions on Reliability, vol. 51, no. 4, pp. 494-504, Dec. 2002. 

7. M. Nourani, A. Attarha and C. Lucas, 
   ``Application of Fuzzy Logic in Resistive Fault Modeling and Simulation,''
   IEEE Transactions on Fuzzy Logic, vol. 10, no. 4, pp. 461-472, Aug. 2002.

6. M. Nourani and C. Papachristou, 
   ``False Path Exclusion in Delay Analysis of RTL Circuits,'' 
   IEEE Transactions on VLSI, vol. 10, no. 1, pp. 30-43, Feb. 2002.

5. H. Mahmoodi-Meimand, A. Afzali-Kushaa and M. Nourani,
   ``Adiabatic Carry Look-Ahead Adder with Efficient Power Clock Generator,''
   IEE Proceedings - Circuits, Devices and Systems,
   vol. 148, no. 5, pp. 229-234, Oct. 2001.  

4. M. Nourani, J. Carletta and C. Papachristou,
   ``Integrated Test of Interacting Controllers and Datapaths,''
   ACM Transactions on Design Automation of Electronic Systems, 
   vol. 6, no. 3, pp. 1-22, July 2001.

3. M. Nourani and C. Papachristou,
   ``Stability-Based Algorithms for High Level Synthesis of Digital ASICs,''
   IEEE Transactions on VLSI, vol. 8, no. 4, pp. 431-434, Aug. 2000.

2. M. Nourani and C. Papachristou, 
   ``Structural Fault Testing of Embedded Cores Using Pipelining,'' 
   Journal of Electronic Testing: Theory and Applications 
   (JETTA), vol. 15, no. 1.2, pp. 129-144, Oct. 1999.

1. C. Papachristou, M. Nourani and M. Spining, 
   ``A Multiple Clocking Scheme for Low Power RTL Design,''
   IEEE Transactions on VLSI, vol. 7, no. 2, pp. 266-276, June 1999.


CONFERENCE PUBLICATIONS
-----------------------

60. M. Nourani and M. Akhbarizadeh,
    ``A Fully Scalable IP Forwarding Engine Based on Partitioned Lookup Table,''
    in Proceedings of the IEEE Globecom Conference,
    (Taipei, Taiwan), pp. ..., Nov. 2002.

59. M. Tehranipour and M. Nourani,
    ``Signal Integrity Loss in SoC's Interconnects:
    A Diagnosis Approach Using Embedded Microprocessor,''
    in Proceedings of the International Test Conference (ITC), 
    (Baltimore, MD), pp. 1093-1102, Oct. 2002.

58. M. Akhbarizadeh and M. Nourani,
    ``Reconfigurable Memory Architecture for Scalable IP Forwarding Engines,'' 
    in Proceedings of the IEEE International Conference on Computer 
    Communications and Networks (ICCCN) (Miami, FL), pp. 432-437, Oct. 2002.

57. M. Tehranipour and M. Nourani, 
    ``Test Optimization of Bus-Structured SoCs Using Embedded Microprocessor,''
    in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 
    (Tulsa, OK), pp. ..., August. 2002.

56. G. Kavipurapu and M. Nourani, 
    ``Switch Fabric Design and Performance Evaluation: Metrics and Pitfalls,''
    in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 
    (Tulsa, OK), pp. ..., August. 2002.

55. S. Nazarian and M. Nourani, 
    ``A Parallel Algorithm for Power Estimation at Gate level,''
    in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 
    (Tulsa, OK), pp. ..., August. 2002.

54. M. Gholipour, A. Afzali-Kusha, M. Nourani and A. Khademzadeh,
    ``An Efficient Asynchronous Pipeline FIFO for Low-Power Applications,''
    in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 
    (Tulsa, OK), pp. ..., August. 2002.

53. R. Dehghani, S. Atarodi, B. Bornoosh, A. Afzali-Kusha and  M.Nourani,
    ``A Reduced Complexity Low Voltage 1-Bit High-Order Digital Delta-Sigma
    Modulator for Fractional-N Frequency Synthesis,''
    in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 
    (Tulsa, OK), pp. ..., August. 2002.

52. S. Fakhraie, M. Tehranipour, M. Movahedin and M. Nourani,
    ``Fast Prototyping of a DSP Core,''
    in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 
    (Tulsa, OK), pp. ..., August. 2002.

51. A. Attarha and M. Nourani,
    ``Signal integrity Fault Analysis Using Reduced-Order Modeling,''
    in Proceedings of the 39th Design Automation Conference (DAC), 
    (New Orleans, LA), pp. 367-370, June 2002.

50. A. Attarha and M. Nourani,
    ``Test Pattern Generation for Signal Integrity Faults on 
    Long Interconnects,''
    in Proceedings of the VLSI Test Symposium (VTS), 
    (Monterey, CA), pp. 336-341, May 2002.

49. M. Nourani and J. Chin,
    ``Testing High-Speed SoCs Using Low-Speed ATEs,''
    in Proceedings of the VLSI Test Symposium (VTS), 
    (Monterey, CA), pp. 133-138, May 2002.

48. F. Fadaie, M. Nourani and B. Forouzande,
    ``Infrared Tracker Robot: Search and Rescue Operations,''
    in Proceedings of the Space 2002 and Robotics 2002 Conferences (ASCE) 
    (Albuquerque, NM), pp. ..., March 2002.

47. M. Akhbarizadeh and M. Nourani,
    ``IP Routing Based on Partitioned Lookup Table,'' 
    in Proceedings of the IEEE International Conference
    on Communications (ICC) (New York, NY), pp. 2263-2267, April 2002.

46. A. Attarha and M. Nourani,
    ``Testing Interconnects for Noise and Skew in Gigahertz SoCs,'' 
    in Proceedings of the International Test Conference (ITC), 
    (Baltimore, MD), pp. 305-314, Oct. 2001.

45. M. Nourani, G. Kavipurapu and R. Gadiraju,
    ``System Requirements for Super Terabit Routing,''
    in Proceedings of IEEE Midwest Symposium on Circuits and 
    Systems (MWSCAS), (Fairborn, OH), pp. 926-929, August. 2001.

44. M. Nourani and A. Attarha,
    ``Built-In Self-Test for Signal Integrity,'' 
    in Proceedings of the 38th Design Automation Conference (DAC), 
    (Las Vegas, Nevada), pp. 792-797, June 2001.

43. A. Attarha and M. Nourani ,
    ``Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs,'' 
    in Proceedings of the VLSI Test Symposium (VTS), 
    (Los Angeles, CA), pp. 111-116, May 2001.

42. A. Attarha and M. Nourani,
    ``The Effect of Gate Orientation on Fault Detection,'' 
    in Proceedings of the International Conference on
    Microelectronics (ICM), (Tehran, Iran), pp. 113-116, Nov. 2000.

41. M. Nourani and C. Papachristou,
    ``An ILP Formulation to Optimize Test Access Mechanism in SoC Testing,'' 
    in Proceedings of the International Test Conference (ITC), 
    (Atlantic City, NJ), pp. 902-910, Oct. 2000.

40. H. Mahmoodi, A. Afzali and M. Nourani,
    ``Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI,'' 
    in Proceedings of the Midwest Symposium on Circuits and
    Systems (MWSCAS) (Lansing, MI), Aug. 2000.

39. M. Nourani, J. Carletta and C. Papachristou,
    ``Synthesis-for-Testability of Controller-Datapath Pairs That Use 
    Gated Clocks,'' in Proceedings of the 37th Design Automation Conference 
    (DAC), (Los Angeles, CA), pp. 613-618, June 2000.

38. A. Attarha, M. Nourani and C. Lucas, 
    ``Modeling and Simulation of Real Defects Using Fuzzy Logic,''
    in Proceedings of the 37th Design Automation Conference (DAC), 
    (Los Angeles, CA), pp. 631-636, June 2000.

37. J. Carletta, C. Papachristou and M. Nourani,
    ``Detecting Undetectable Controller Faults Using Power Analysis,'' 
    in Proceedings of the Design Automation and Test in Europe
    Conference (DATE), (Paris, France), pp. 723-728, March 2000.

36. M. Nourani and C. Papachristou,
    ``Test Access Mechanism for Core Based System-on-Chip,''
    Seventh International Test Synthesis Workshop, (Santa Barbara, CA), 
    March 2000.

35. O. Nasibi, M. Nourani, M. Fakhraie, and A. Ghalambor, 
    ``Multi-Access Integrated Memory Management for Deeply Pipelined 
    Processors,'' in Proceedings of the 11th International Conference 
    on Microelectronics, (Kuwait City, Kuwait), pp. 285-289, Nov. 1999.

34. C. Papachristou, F. Martin and M. Nourani,
    ``Microprocessor Based Testing for Core-Based System-on-Chip,'' 
    in Proceedings of the 36th Design Automation Conference (DAC), 
    (New Orleans, Louisiana), pp. 586-591, June 1999.

33. J. Carletta, M. Nourani and C. Papachristou, 
    ``Synthesis of Controllers for Full Testability of Integrated 
    Datapath-Controller Pairs,'' 
    in Proceedings of the Design Automation and Test 
    in Europe Conference (DATE), (Munich, Germany), pp. 278-282, March 1999.

32. A. Attarha, M. Nourani and M. Zakeri, 
    ``A High Performance Low Power Multiplier for DSP Applications,''
    in Proceedings of the ICEE-99 Conference,
    (Tehran, Iran), pp. 37-44, April 1999.

31. A. Attarha, M. Nourani and C. Lucas, 
    ``A Fuzzy Logic Approach for Fault Simulation of Unconventional
    Defects in VLSI Circuits,''
    in Proceedings of the ICEE-99 Conference,
    (Tehran, Iran), pp. 45-53, April 1999.

30. H. Motallebpoor, C. Lucas, P. Jabbehdar and M. Nourani, 
    ``Data Flow Graph Scheduling Using Genetic Algorithms,'' 
    in Proceedings of the ICEE-99 Conference,
    (Tehran, Iran), pp. 125-132, April 1999.

29. O. Nasibi and M. Nourani, 
    ``A Testable Datapath Generation Method with Minimum Test Overhead,'' 
    in Proceedings of the CSICC-98 Conference, 
    (Tehran, Iran), pp. 188-193, Dec. 1998.

28. A. Attarha and M. Nourani, 
    ``An Accurate Digital Circuit Simulation Using Fuzzy Logic,'' 
    in Proceedings of the CSICC-98 Conference, 
    (Tehran, Iran), pp. 219-224, Dec. 1998.

27. M. Nourani and C. Papachristou, 
    ``Parallelism in Structural Fault Testing of Embedded Cores,'' 
    in Proceedings of the VLSI Test Symposium (VTS), 
    (Monterey, California), pp. 15-20, April 1998.

26. A. Attarha and M. Nourani, 
    ``Fault Simulation of Digital Circuits Using Fuzzy Logic,''
    in Proceedings of the ICEE-98 Conference, 
    (Tehran, Iran), pp. 117-122, April 1998.

25. A. Alimohammad and M. Nourani, 
    ``Minimal BIST Insertion Using Test Metrics,''
    in Proceedings of the ICEE-98 Conference, 
    (Tehran, Iran), pp. 111-116, April 1998.

24. H. Torabi and M. Nourani, 
    ``UT-BEST: An Environment for Developing Synthesis Algorithms,''
    in Proceedings of the ICEE-98 Conference, 
    (Tehran, Iran), pp. 99-104, April 1998.

23. M. Mahmoudian and M. Nourani, 
    ``Using Switching Activity Metric for Power Estimation of CMOS Circuits,''
    in Proceedings of the ICEE-98 Conference, 
    (Tehran, Iran), pp. 47-51, April 1998.

22. M. Nourani, 
    ``Fault Classification for Embedded-Core Testing,''
    in Proceedings of the ICEE-98 Conference, 
    (Tehran, Iran), pp. 41-46, April 1998.

21. M. Nourani and C. Papachristou, 
    ``A Bypass Scheme for Core-Based System Fault Testing,'' 
    in Proceedings of the Design Automation and Test in Europe 
    Conference (DATE), poster presentation, 
    (Paris, France), pp. 979-980, Feb. 1998.

20. M. Nourani and H. Nikmehr, 
    ``Cache Simulation Based on Working Set Shift,'' 
    in Proceedings of the CSICC-97 Conference, 
    (Tehran, Iran), pp. 215-220, Dec. 1997.

19. A. Alimohammad and M. Nourani, 
    ``Testability Metrics Definition Using Behavioral and Structural Analysis,'' 
    in Proceedings of the CSICC-97 Conference, 
    (Tehran, Iran), pp. 408-413, Dec. 1997.

18. M. Nourani, J. Carletta and C. Papachristou,
    ``A Scheme for Integrated Controller-Datapath Fault Testing,'' 
    in Proceedings of the 34th Design Automation Conference (DAC), 
    (Anaheim, California), pp. 546-551, June 1997.

17. H. Torabi and M. Nourani, 
    ``UT-BEST: An Environment for Automatic Behavioral Synthesis,''
    in Proceedings of the ICEE-97 Conference, 
    (Tehran, Iran), pp. 125-132, April 1997.

16. M. Tajmiri and M. Nourani, 
    ``Parallel Execution of Speech Recognition Algorithms,''
    in Proceedings of the ICEE-97 Conference, 
    (Tehran, Iran), pp. 67-76, April 1997.

15. M. Nourani and C. Papachristou, 
    ``Structural Test Insertion Using Behavioral Test Analysis,'' 
    in Proceedings of the European Design & Test Conference (ED&TC), 
    (Paris, France), pp. 64-68, March 1997.

14. M. Nourani and C. Papachristou, 
    ``Extracting Test Behavior for Minimal BIST Insertion,'' 
    in Proceedings of the CSICC-96 Conference, 
    (Tehran, Iran), pp. 37-42, Dec. 1996.

13. M. Nourani and C. Papachristou, 
    ``False Path Exclusion in Delay Analysis of RTL-Based
    Datapath-Controller Designs,'' 
    in Proceedings of the European Design Automation Conference (EURO-DAC), 
    (Geneva, Switzerland), pp. 336-341, Sept. 1996.

12. C. Papachristou, M. Spining and M. Nourani, 
    ``An Effective Power Management Scheme for RTL Design Based on
    Multiple Clocks,'' 
    in Proceedings of the 33th Design Automation Conference (DAC), 
    (Las Vegas, Nevada), pp. 337-342, June 1996.

11. M. Nourani and C. Papachristou, 
    ``Avoiding False Paths Caused by Resource Binding in RTL Delay Analysis,'' 
    in Proceedings of the ISCAS-96 Conference, 
    (Atlanta, Georgia), pp. 102-106, May 1996.

10. M. Nourani and C. Papachristou, 
    ``Test Controller Synthesis by Adding a Piggyback Logic,'' 
    in Proceedings of the ICEE-96 Conference, 
    (Tehran, Iran), pp. 463-470, April. 1996.

9.  M. Nourani and C. Papachristou, 
    ``A Power Estimation Algorithm for RTL Datapath,'' 
    in Proceedings of the CSICC-95 Conference, 
    (Tehran, Iran), pp. 15-20, Dec. 1995.

8.  C. Papachristou, M. Spining and M. Nourani, 
    ``A Multiple Clocking Scheme for Low Power RTL Design,'' 
    in Proceedings of the  International Symposium on 
    Low Power Electronics & Design (ISLPED), 
    (Dana Point, California), pp. 27-32, April 1995.

7.  H. Harmanani, C. Papachristou, J. Carletta and M. Nourani,
    ``A Method for Testability Insertion at the RTL - 
    Behavioral and Structural,'' 
    First International Test Synthesis Workshop,
    (Santa Barbara, CA), pp. 45-49, May 1994.

6.  M. Nourani and C. Papachristou, 
    ``A Layout Estimation Algorithm for RTL Datapath,'' 
    in Proceedings of the 30th Design Automation Conference (DAC), 
    (Dallas, Tx), pp. 285-291, June 1993.

5.  C. Papachristou, H. Harmanani and M. Nourani, 
    ``An Approach for Redesigning in Data Path Synthesis,''
    in Proceedings of the 30th Design Automation Conference (DAC), 
    (Dallas, Tx), pp. 419-425, June 1993.

4.  M. Nourani, C. Papachristou and Y. Takefuji, 
    ``A Neural Network Based Algorithm for the Scheduling Problem 
    in High-Level Synthesis,'' 
    in Proceedings of the European Design Automation Conference (EURO-DAC), 
    (Hamburg, Germany), Spp. 341-346, ept. 1992.

3.  H. Harmanani, C. Papachristou, S. Chiu and M. Nourani, 
    ``SYNTEST: An Environment for System-Level Design for Test,'' 
    in Proceedings of the European Design Automation Conference (EURO-DAC), 
    (Hamburg, Germany), pp. 402-407, Sept. 1992.

2.  M. Nourani and C. Papachristou, 
    ``Move Frame Scheduling Based on Liapunov Stability
    Theorem for the Automated Synthesis of Digital Systems,'' 
    in Proceedings of the 29th Design Automation Conference (DAC), 
    (Anaheim, CA), pp. 99-105, June 1992.

1.  M. Nourani, C. Papachristou and Y. Takefuji, 
    ``A Parallel Algorithm for Scheduling Problem Based on Hopfield 
    Model for the Automated Synthesis of Digital Systems,''  
    IJCNN, Poster Presentation, 
    (Seattle, WA), pp. 910, July 1991.