Abstract- The main contribution of this project is a methodology to design scalable and flexible multi-search per cycle routing engines based on a partitioned TCAM architecture. Our two-stage architecture will work effectively for dynamic and unpredicted Internet traffic. The first stage targets the design of a small and flexible lookup shortcut table that works similar to the prefix cache. The shortcomings of the current state of the art are alleviated by storing the prefixes directly with no need for routing table preprocessing. With the completion of this stage, we will have a small but efficient shortcut table that can be duplicated inside a search engine with negligible cost overhead. The outcome of this stage will then be used to augment the partitioned search engine in the next stage. The goal of the second stage is to exploit the inherent parallelism of partitioned TCAM search engines to improve throughput by searching multiple partitions simultaneously. We plan to reach this goal even for dynamic and unpredictable incoming traffic patterns. This is achieved by avoiding contentions using small shortcut table units that accompany block selectors. This shortcut tables dynamically store the most popular prefixes, which are the cause of most contentions. The resulting parallelism that comes at negligible cost, also allows multi-threaded network processors to reduce the number of wait states in their search code pass and further improve the advantage of hardware-based search engines over software search algorithms.
Abstract- As we approach 100nm technology, the impact of interconnect on signal integrity is becoming one of the main concerns in testing gigahertz system-on-chips (SoCs). Voltage distortion (noise) and delay violations (skew) contribute to signal integrity loss and ultimately functional error, performance degradation, shorter life and reliability problems. This research proposes a methodology to model and test signal integrity in deep-submicron high-speed interconnects that bind the internal cores in a SoC. The following issues are being explored: (a) the development of a unified integrity fault model, independent of technology, that includes various problems occurring on the SoC's high-speed interconnects such as crosstalk, overshoot, skew, etc.; (b) the establishment of a test generation technique that finds test patterns to stimulate maximal (worst case) integrity loss on the interconnect network; (c) the implementation of noise detector (ND) and skew detector (SD) cells, to detect noise and skew violations (integrity loss) over a period of operation; and (d) the design of a cost- and time-efficient readout architecture to transfer the integrity information that ND and SD cells accumulate. As part of educational plan, we are: 1) developing a two course sequence on ASIC/SoC design and test with emphasis on high-frequency issues; 2) involving undergraduate students in general, and minorities in particular, in VLSI/ASIC/SOC test research. 3) advocating for greater CAD tool use in early stage of CE/EE curriculum.
Abstract- Rapid growth of Internet has created a challenge for communication engineers to address the data packet-based routing problem. Packet routing is the chosen communication strategy in many applications such as Internet and wireless networks. Routing is a multi-dimensional problem that requires innovative solutions in different levels of design hierarchy including algorithmic, logic, system and VLSI levels. In this work we investigate a novel router-on-chip (RoC) design to satisfy the Internet's huge appetite for large routing tables, increased traffic, higher speed and the migration to the IPv6 format. Three main objectives in this project are: 1) programmability, 2) flexibility and 3) high-speed. the first two objectives are partially realized by an efficient IP routing methodology and architecture. This is achieved by partitioning the lookup table into the smaller ones for each output port and allowing a routing engine to process them in parallel. This effectively reduces the complexity of finding ``the longest prefix match''problem to ``a prefix match'' problem. Moreover, it significantly alleviates the need for a large/slow switch fabric and its controller that in many router designs have become the bottleneck. The second and third goals are realized by integrating various cores (e.g. IP router engine, partitioned memory modules, etc.) within a programmable system-on-chip. We estimate that the VLSI implementation of such chip, called router-on-chip (RoC), using 0.25 u m or better technology easily provides aggregated transfer rate of 2.5 Terabit per second that is equivalent to 64 OC-768 or 256 OC-192. From design point of view, this project addresses one of the main challenges in high-speed packet-based communication. High speed routing applications such as telecommunication, satellite communication and ultra-speed Internet networking can immensely benefit from this architecture.
Abstract- The primary objective of this research is to design energy efficient VLSI circuits and architectures for applications in telecommunications and digital signal processing (DSP). With the growing popularity of battery powered portable applications like personal communication systems, wireless/mobile computing etc., high performance circuits that dissipate less power (energy efficient) are gaining importance. This research explores two new revolutionary techniques, i.e. (i) Adiabatic Logic and (ii) vMOS (neuron-MOS) based Threshold Gate, at the transistor and gate levels. Using these techniques we will design some widely-used communication cores, study tradeoffs among power, speed and area; and compare the results with traditional low-power CMOS design techniques. We concentrate on the design of basic building blocks for communications and DSP systems. These basic building blocks can be used in conjunction with DSPs to implement widely-used algorithms in hardware. The aim of this project will be to implement critical building blocks of the third generation wireless communications systems (in particular, CDMA systems) which cannot be implemented using DSP architectures. In particular, ACS (Add-Compare-Select), often used in conventional butterfly structure, are the most power-hungry macrocell in many of communication systems such as coding and decoding blocks, the PN code acquisition and tracking, high-speed channel estimation blocks, etc.