Main Activities & Publications
Acknowledgment and Disclaimer:
All materials in this page are based upon work fully or partially
supported by the National Science Foundation under Grant No. 0130513.
Any opinions, findings, and conclusions or recommendations expressed in these
materials are those of the author(s) and do not necessarily reflect the views
of the National Science Foundation.
Signal Integrity Fault Modeling & Analysis
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M. Nourani and A. Radhakrishnan,
``Power-Supply Noise in SoCs: ATPG, Estimation and Control,''
in Proceedings of the International Test Conference (ITC),
(Austin, TX), pp. 22.1.1-22.1.10, Nov. 2005.
Full Article
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M. Nourani and A. Attarha,
``Signal Integrity: Fault Modeling and Testing in
High-Speed SoCs,''
Journal of Electronic Testing:
Theory and Applications (JETTA), pp. 539-554, 2002.
Full Article
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M. Nourani and A. Attarha,
``Detecting Signal Overshoots for Reliability Analysis in
High-Speed SoCs,''
IEEE Transactions on Reliability,
vol. 51, no. 4, pp. 494-504, Dec. 2002.
Full Article
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M. Nourani, A. Attarha and C. Lucas,
``Application of Fuzzy Logic in Resistive Fault Modeling and Simulation,''
IEEE Transactions on Fuzzy Logic,
vol. 10, no. 4, pp. 461-472, Aug. 2002.
Full Article
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M. Tehranipour and M. Nourani,
``Signal Integrity Loss in SoC's Interconnects:
A Diagnosis Approach Using Embedded Microprocessor,''
in Proceedings of the International Test Conference (ITC),
(Baltimore, MD), pp. 1093-1102, Oct. 2002.
Full Article
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A. Attarha and M. Nourani,
``Signal integrity Fault Analysis Using Reduced-Order Modeling,''
in Proceedings of the 39th Design Automation Conference (DAC),
(New Orleans, LA), pp. 367-370, June 2002.
Full Article
Enhanced DFT Techniques
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M. Tehranipour, N. Ahmed and M. Nourani,
``Testing SoC Interconnects for Signal
Integrity Using Extended JTAG Architecture,''
in IEEE Transactions on Computer Aided Design,
vol. 23, no. 5, pp. 800-811, May 2004.
Full Article
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M. Tehranipour, N. Ahmed, M. Nourani,
``Testing SoC Interconnects for Signal Integrity Using Boundary Scan,''
in Proceedings of the VLSI Test Symposium (VTS),
(Napa Valley, CA), pp. 158-163, April 2003.
Full Article
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N. Ahmed, M. Tehranipour and M. Nourani,
``Extending JTAG for Testing Signal Integrity in SoCs,''
in Proceedings of the Design Automation and Test
in Europe Conference (DATE),
(Munich, Germany), pp. 218-223, March 2003.
Full Article
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A. Attarha and M. Nourani,
``Testing Interconnects for Noise and Skew in Gigahertz SoCs,''
in Proceedings of the International Test Conference (ITC),
(Baltimore, MD), pp. 305-314, Oct. 2001.
Full Article
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M. Nourani and A. Attarha,
``Built-In Self-Test for Signal Integrity,''
in Proceedings of the 38th Design Automation Conference (DAC),
(Las Vegas, NV), pp. 792-797, June 2001.
Full Article
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A. Attarha and M. Nourani,
``Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs,''
in Proceedings of the VLSI Test Symposium (VTS),
(Los Angeles, CA), pp. 111-116, May 2001.
Full Article
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N. Ahmed, M. Tehranipour, D. Zhou and M. Nourani,
``Frequency Driven Repeater Insertion for Deep Submicron,''
in Proceedings of the International Symposium on Circuits
and Systems (ISCAS),
(Vancouver, Canada), pp. V181-V184, May 2004.
Full Article
Test Pattern Generation
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M. Nourani, M. Tehranipoor and N. Ahmed,
``Pattern Generation and Estimation for Power Supply Noise Analysis,''
in Proceedings of the VLSI Test Symposium (VTS),
(Palm Springs, CA), pp. 439-444, May 2005.
Full Article
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M. Tehranipour, N. Ahmed and M. Nourani,
``Multiple Transition Model and Enhanced Boundary Scan Architecture
to Test Interconnects for Signal Integrity,''
in Proceedings of International Conference on
Computer Design (ICCD) (San Jose, CA), pp. 554-559, Oct. 2003.
Full Article
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A. Attarha and M. Nourani,
``Test Pattern Generation for Signal Integrity Faults
on Long Interconnects,''
in Proceedings of the VLSI Test Symposium (VTS),
(Monterey, CA), pp. 336-341, May 2002.
Full Article
Test Data Compression
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M. Tehranipour, M. Nourani and K. Chakrabarty,
``Nine-Coded Compression Technique for Testing Embedded Cores in SoCs,''
in IEEE Transactions on VLSI, vol. 13, no. 6, pp. 719-731, June 2005.
Full Article
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M. Nourani and M. Tehranipour,
``RL-Huffman Encoding for Test Compression and Power
Reduction in Scan Applications,''
in ACM Transactions on Design Automation of
Electronic Systems, vol. 10, no. 1, pp. 91-115, Jan. 2005.
Full Article
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M. Tehranipour, M. Nourani and K. Chakrabarty,
``Nine-Coded Compression Technique with Application to
Reduced Pin-Count Testing and Flexible On-Chip Decompression,''
in Proceedings of the Design Automation and Test
in Europe Conference (DATE),
(Paris, France), pp. 1284-1289, Feb. 2004.
Full Article
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M. Tehranipour, M. Nourani, K. Arabi and A. Afzali-Kusha,
``Mixed RL-Huffman Encoding for Power Reduction and Data
Compression in Scan Test,''
in Proceedings of the International Symposium on Circuits
and Systems (ISCAS),
(Vancouver, Canada), pp. II681-II684, May 2004.
Full Article
Power Consumption During Test
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M. Tehranipoor, M. Nourani and N. Ahmed,
``Low Transition LFSR for BIST-Based Applications,''
in Proceedings of Asian Test Symposium (ATS'05),
(Kolkata, India), pp. ..., Dec. 2005.
Full Article
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K. Baker and M. Nourani,
``Interconnect Test Pattern Generation Algorithm for Meeting
Device and Global SSO Limits with Safe Initial Vectors,''
in Proceedings of the International Test Conference (ITC),
(Charlotte, NC), pp. 163-172, Oct. 2004.
Full Article
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J. Chin and M. Nourani,
``SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance,''
in Proceedings of the Design Automation and Test
in Europe Conference (DATE),
(Paris, France), pp. 710-711, Feb. 2004.
Full Article
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M. Nourani and J. Chin,
``Power-Time Tradeoff in Test Scheduling for SoCs,''
in Proceedings of International Conference on
Computer Design (ICCD) (San Jose, CA), pp. 548-553, Oct. 2003.
Full Article
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N. Ahmed, M. Tehranipour and M. Nourani,
``Low Power Pattern Generation for BIST Architecture,''
in Proceedings of the International Symposium on Circuits
and Systems (ISCAS),
(Vancouver, Canada), pp. II689-II692, May 2004.
Full Article
Test Scheduling for SoCs
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J. Chin and M. Nourani,
``FITS: An Integrated ILP-Based Test Scheduling Environment,''
in IEEE Transactions on Computers, vol. 54, no. 12, pp. 1598-1613,
Dec. 2005.
Full Article
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M. Tehranipour, M. Nourani, S. Fakhraie, M. Movahedin and Z. Navabi,
``Embedded Test for Processor and Memory Cores in System-on-Chips,''
in International Journal of Scientia Iranica, vol. 10, no. 4, Sept. 2003.
Full Article
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M. Nourani, J. Carletta and C. Papachristou,
``Integrated Test of Interacting
Controllers and Datapaths,''
ACM Transactions on Design Automation of
Electronic Systems, vol. 6, no. 3, pp. 1-22, July 2001.
Full Article
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M. Tehranipour, M. Nourani, S. Fakhraie and A. Afzali-Kusha,
``Systematic Test Program Generation for SoC Testing Using Embedded Processor,''
in Proceedings of the International Symposium on Circuits
and Systems (ISCAS),
(Bangkok, Thailand), pp. V541-V544, May 2003.
Full Article
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M. Tehranipour, M. Nourani, S. Fakhraie and C. Papachristou,
``Test Optimization of Bus-Structured SoCs Using Embedded Microprocessor,''
in Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS),
(Tulsa, OK), pp. I168-I171, Aug. 2002.
Full Article
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M. Nourani and J. Chin,
``Testing High-Speed SoCs Using Low-Speed ATEs,''
in roceedings of the VLSI Test Symposium (VTS),
(Monterey, CA), pp. 133-138, May 2002.
Full Article
Massive Parallelism in Testing
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S. Vengatachalam, M. Nourani and M. Akhbarizadeh,
``TAN: A Packet Switched Network for VLSI Testing,''
in Proceedings of the IEEE International Conference on Computer
Communications and Networks (ICCCN) (Dallas, TX), pp. 605-608, Oct. 2003.
Full Article
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M. Nourani and S. Vengatachalam,
``ZIP-ATE: Zero-to-Infinity Pins ATE Using Packet Switched Network,''
Future of ATE Workshop (FATE)
(Charlotte, NC), Oct. 2003.
Full Article
Low-Power Memory Architecture
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D. Vijayasarathi, M. Nourani, M. Akhbarizadeh and P. Balsara,
``Ripple-Precharge TCAM:
A Low-Power Solution for Network Search Engines,''
in Proceedings of International Conference on
Computer Design (ICCD), (San Jose, CA),
pp. 243-248, Oct. 2005.
Full Article
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M. Akhbarizadeh, M. Nourani, D. Vijayasarathi and P. Balsara,
``PCAM: A Ternary CAM
Optimized for Longest Prefix Matching Tasks,''
in Proceedings of International Conference on
Computer Design (ICCD)-Received Best Paper Award, (San Jose, CA),
pp. 6-11, Oct. 2004.
Full Article