VLSI CAD Tools and Technology Files

  CAD tools Setup at UTD: In order to use CAD tools from Cadence, HSpice, and NanoSim you need to make
      sure that all Unix environment variables are correctly. You may do this by following the instructions for     
      VLSI CAD Software Setup . 
    

Schematic, Layout and Simulation Flow

  Schematic and Layout using Cadence Tools

For Cadence tools, we will use the 0.13μm CMOS technology available at UTD. The following are the steps that we will follow in our design:

• Setup the files required to start Cadence tools. This needs to be done only once initially.

• Start Cadence and create a design library. You can add all the new cells you create in this library.

• Draw the circuit using schematic entry.

  • Schematic Tutorial 1.
  • Schematic Tutorial 2.
  • Hspice netlist from Schematic.
  • Creating symbol view.
  • You can directly run simulations on the schematic using Spectre Simulation. Spectre model library is located at: /home/cad/kits/IBM_CMRF8SF-LM013/IBM_PDK/cmrf8sf/V1.2.1.2LM/Spectre/models/allModels.scs

• Draw the layout using Virtuoso .

  • Layout Tutorial.
  • Printing a hardcopy.
  • Inverter Layout Example.
  • Some Layout tips.
  • Here are some files related to design rules:  CA-M1 Rule, RX-PC Rule
  • Detailed designed rules can be found in /home/cad/kits/IBM_CMRF8SF-LM013/IBM_PDK/cmrf8sf/relLM/doc/cmr8sf.design_manual.pdf

• Design verification using Assura .

  • Design Rule Checker: DRC Tutorial.
  • Layout versus Schematic check: LVS Tutorial.
  • Hierarchical LVS Tutorial.

• Create the SPICE netlist using parasitic extraction. PEX Tutorial.

• A list of some Cadence ICFB Hotkeys

• Simulate the circuit using HSPICE or Nanosim as described below.

     Step-by-Step Cadence tools guide from UT Austin

  Simulation using Nanosim and HSPICE

• Circuit Simulation using NanoSim and CosmosScope

• Circuit Simulation using HSPICE and CosmosScope

• Example files for Nanosim and Hspice simulation

• Example of Parameterized Hspice simulation files

          Detailed user guides and other documentation for these simulators can be found in the next section.

  Simulation Tools: NanoSim

• Circuit Simulation using NanoSim and CosmosScope
  • NanoSim Users Guide 
  • NanoSim Quick Reference
  • CosmosScope Documentation

  Simulation Tools: HSpice

• Circuit Simulation using HSPICE and CosmosScope
  • HSPICE Online Documentation
  • University of Wisconsin HSPICE Tutorials
  • University of Wisconsin Tutorial on Digital Design using HSPICE
  • HSPICE Quick Reference Guide
  • Tips on using HSPICE from UC Berkeley
   
  • CosmosScope Documentation
  • Additional examples are provided in the directory /home/cad/vlsi/tutorials

NCSU Flow with the 0.18um CMOS Technology

• For other Cadence tutorials from NCSU, you can use theNCSU Cadence Design Kit (CDK)  (available from North Carolina State Univ.).  These tutorials are for 0.18μm CMOS  technology.  In order to run these tutorials, create a new Cadence working directory (in your home directory) and copy the following files:

  /home/cad/vlsi/NCSU-CDK/local/.cdsenv
  /home/cad/vlsi/NCSU-CDK/local/.cdsinit
  /home/cad/vlsi/NCSU-CDK/local/.simrc 
  /home/cad/vlsi/NCSU-CDK/local/cds.lib
  Before you do this make sure that your environment variables are
  set correctly as mentioned in the CAD tools setup above.

• Invoke Cadence tools in your working directory by typing  icfb   at the command prompt.  You should now get the Cadence CIW (popup window) on your screen.
• Cadence Tutorials from WPI:  http://www.vlsi.wpi.edu/cds/
• NCSU Cadence Tutorials:  http://www.eda.ncsu.edu/wiki/Tutorial:Contents
• Use the following tutorial to understand the Cadence design flow:  http://vlsi.wpi.edu/cds
• Cadence tutorials from Virginia Tech:  http://www.vtvt.ece.vt.edu/vlsidesign/tutorial/Cadence_digi_intro.php
• Generating SPICE3 netlist from Cadence
• Note:  The netlist file generated does not have proper device names.  You can either edit netlist file manually and change all TSMC20P to pfet and TSMC20N to nfet or you can add these two statements at the top of the netlist file:
    .MSELECT tsmc20P pfet
    .MSELECT tsmc20N nfet

  MOSIS Fabrication Services

• MOSIS Homepage
• MOSIS CMOS Design Rules
• MOSIS Technology codes and Layer Maps for 0.18um process (use deep submicron version).

  CMOS Technology Information

• SCMOS Design Rules from MOSIS, ver. 8.0
• 0.13um CMOS HSPICE device models  (/home/cad/ee6325/models/hspice/cmos0.13um.model)