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Jitter-Tolerance and Blocker-Tolerance of Analog-to-Digital Converters for SAW-Less Multi-Standard Receivers by Dr. Sebastian Hoyos, TAMU
Friday, May 31, 2013
1 p.m. - 2 p.m. Location: ECSS 3.503


Continuous-time (CT) ΔƩ analog-to-digital converters (ADCs) have gained significant attention in wideband receivers, because of their amenability to operate at a higher-speed with lower power consumption compared to discrete-time counterparts, inherent anti-aliasing, and robustness to sampling errors in the quantizer. However, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. A simple hybrid DAC solution is presented that achieves tolerance to DAC pulse-width jitter errors by spectrally shaping the jitter induced errors in the feedback DAC. The proposed technique features an efficient combination between the conventional rectangular-pulse switched-current (SI) DAC and a discrete-time switched-capacitor (SC) DAC to achieve spectral shaping for the jitter induced error in the modulator’s feedback signal. As a prove of concept, a 384 MHz second-order single-bit CT ΔƩ modulator for WCDMA baseband channel of 1.92 MHz has been designed using the proposed feedback hybrid DAC structure. The ΔƩ modulator is designed in a 1.2 V, 90nm, IBM 9LP CMOS process. A maximum signal-to-noise-plus-distortion ratio (SNDR) of 68 dB over a 1.92 MHz bandwidth is achieved, while consuming 3.44 mW. Simulation results show 20 dB robustness to pulse-width jitter (PWJ) over the commonly used non-return-to-zero DACs.


Sebastian Hoyos received the B.S. degree in electrical engineering from Pontificia Universidad Javeriana (PUJ), Bogota, Colombia, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from the University of Delaware, Newark, in 2002 and 2004, respectively. He was with Lucent Technologies Inc., Bogota, Colombia, from 1999 to 2000 for the Andean region in South America. Simultaneously, he was a lecturer with PUJ, where he lectured on microelectronics and control theory. During his M.S. and Ph.D. studies, he was with PMC-Sierra Inc., the Delaware Research Partnership Program, and the Army Research Laboratory Collaborative Technology Alliance in Communications and Networks. He was a Postdoctoral Researcher (2004-2006) with the Berkeley Wireless Research Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. He joined Texas A&M University, College Station, TX in 2006 where he is currently an Associate Professor with the Department of Electrical and Computer Engineering. His research interests include telecommunication systems, digital signal processing, and analog and mixed-signal processing and circuit design.

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Donna Kuchinski, 972-883-5556
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