1 p.m. - 2 p.m. Location: ECSS 3.503
SAR ADCs are not only highly effective by themselves but also form critical building blocks of pipeline ADCs and interleaved SAR ADC arrays. Interleaving of SAR ADCs delivers very high sampling speeds and good energy efficiency. However, interleaving of multiple SAR ADCs poses significant challenges due to the large area needed. A particular problem is that interleaving artifacts are exacerbated by die size. The Charge-Injection Cell Based DAC SAR ADC (ciSAR ADC) is a very compact SAR ADC architecture and achieves excellent energy efficiency. A prototype, fabricated in 40nm CMOS, occupies 0.00058mm2 and consumes 1.26 mW from a 1V supply. The measured ENOB is above 5.46b across input frequencies spanning from 30MHz to 500MHz, sampled at 1GS/s. The area is 52% of the closest competitor and the Walden FoM is measured at 28.6fJ/conv-step.
The SAR assisted pipeline technique facilitates a large stage sub-ADC resolution and removes the sampling mismatch between the MDAC and the sub-ADC. For the same overall ADC resolution, the SAR-assisted pipeline architecture also has advantages compared to the conventional SAR architecture. In particular, for moderately-high resolution (e.g. 12 bits), comparator noise performance is challenging in a conventional SAR ADC. On the other hand, the comparator noise requirement is greatly relaxed in the SAR sub-ADCs of a comparable resolution SAR-assisted pipeline ADC. The cascoded telescopic OTA based SC residue amplifier has been the workhorse of conventional pipeline and SAR-assisted pipeline ADCs. However, the conventional OTA structure consumes a lot of power and has a limited output swing. As an alternative to the OTA, the ring amplifier has the advantages of energy efficient slew-based charging. It generates a near rail-to-rail output swing, and recent ring amplifiers are robust to PVT variation. A prototype 50MS/s 13b ring-amplifier-based SAR-assisted pipeline ADC, employs a 6b first-stage SAR ADC, and an 8b second-stage SAR sub-ADC
The third part of the talk deals with a bi-directional neural interface chip that employs stimulation artifact cancellation to allow concurrent neural recording and stimulation. This capability significantly improves the performance of brain machine interfaces for treatment of disease. In order to further suppress cross-channel common-mode noise, we incorporated a novel common average referencing (CAR) circuit in conjunction with range-adapting (RA) SAR ADC for low-power implementation. The fabricated prototype attenuates stimulation artifacts by up to 42 dB and suppresses common noise among channels by up to 39.8 dB at 330 nW and in an area of 0.17 mm2 per channel.
Michael P. Flynn received the Ph.D. degree from Carnegie Mellon University in 1995. He received the B.E. and M.Eng.Sc. degrees from University College Cork, Ireland in 1988 and 1990, respectively. From 1988 to 1991 he was with the National Microelectronics Research Centre in Cork, Ireland. He was with National Semiconductor in Santa Clara, CA, from 1993 to 1995 and from 1995 to 1997 he was a Member of Technical Staff with Texas Instruments, Dallas, TX. During the four-year period from 1997 to 2001, he was with Parthus Technologies, Cork, Ireland. Dr. Flynn joined the University of Michigan in 2001 and is currently Professor. His technical interests are in data conversion, RF circuits, serial transceivers and biomedical systems.
Michael Flynn is an IEEE Fellow and a 2008 Guggenheim Fellow. He has served on the Technical Program Committees of the International Solid State Circuits Conference (ISSCC), the Symposium on VLSI Circuits and the Asian Solid-State Circuits Conference (ASSCC) and the European Solid-State Circuits Conference. He was a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He was Editor-in-Chief of the IEEE Journal of Solid-State Circuits from 2013 to 2016
Donna Kuchinski, 972-883-5556
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