1 p.m. - 2 p.m. Location: ECSS 3.503
David Blaauw received his Ph.D. in computer science from the University of Illinois at Urbana-Champaign in 1991. Until August 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of the High Performance Design Technology group and won the Motorola Innovation award. Since August 2001, he is a professor at the University of Michigan. He has published over 500 papers, has received numerous best paper awards and nominations, and holds 60 patents. He has investigated adaptive computing to re-duce margins and improve energy efficiency using a new approach he pioneered, called Razor, for which he received the Richard Newton GSRC Industrial Impact Award and IEEE Micro annual Top-Picks award. He has extensive re-search in ultra-low-power computing using subthreshold computing and analog circuits for millimeter sensor systems and for high-end servers, his research group and collabora-tors introduced so-called near-threshold computing, which has become a common concept in semiconductor design. This work led to a complete sensor node design with record low power consumption, which was selected by the MIT Technology Review as one of the year’s most significant innovations. Most recently, he has pursued research in cog-nitive computing using analog, in-memory neural-networks. He serves on the IEEE International Solid-State Circuits Conference’s technical program committee. He is an IEEE Fellow and received the 2016 SIA-SRC faculty award for lifetime research contributions to the U.S. semiconductor industry.
Small form factor, battery-operated sensing systems have very low activity rates and power down their mem-ories during inactive periods to save power, storing data in non-volatile memory. However, conventional non-volatile memories such as flash use high voltages and long duration write operations, causing high energy per bit for writing (> 100pJ/b). Unlike flash, Ferroelectric RAM (FRAM) has significantly faster write times and us-es nominal voltages to write, both of which reduce write energy making it appealing to IoT applications.
In this presentation we present an FRAM design which uses charge recycling (or adiabatic design) to further reduce read and write energy. It leverages the observa-tion that the energy dissipation in FRAM chiefly comes from charging/discharing the large capacitance of the ferroelectric element (~10s of fF), which can be recycled using a resonant clock. This approach increases energy efficiency by 3× compared to non-adiabatic operation and the proposed 130nm 256x80 FRAM memory achieves lowest in-class write energy of 0.99pJ/bit and read energy of 0.4pJ/bit. It achieves 102Mbps through-put at a low operating voltage of 1V (compared to 1.5V nominal) making it compatible with low power IoT applications.
Donna Kuchinski, 972-883-5556
Questions? Email me.