1 p.m. - 2 p.m. Location: ECSS 3.503
Abstract: Clock and data recovery (CDR) is a quintessential function that needs to be performed in all serial communication systems. As data rates increase, the implementation of CDR circuits is becoming very challenging. Classical techniques based on 2x oversampling are becoming inefficient as they require multiple clock phases at very high frequencies. In this e-workshop, I’ll present alternative methods that use baud- and sub-baud-rate architectures. I will begin with a description of baud-rate CDR principles and will extend them to implementing sub-baud-rate CDRs that can recover clock and data using only a quarter-rate clock. I’ll then present circuit implementation details and conclude with the presentation of experimental results obtained from a prototype CDR.
Bio: Pavan Hanumolu is currently a Professor in the Department of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign. He received the Ph.D. degree from the School of Electrical Engineering and Computer Science at Oregon State University, in 2006, where he subsequently served as a faculty member till 2013. Dr. Hanumolu’s research interests are in energy-efficient integrated circuit implementation of analog and digital signal processing, sensor interfaces, wireline communication systems, and power conversion.
Donna Kuchinski, 972-883-5556
Questions? Email me.