Comet Calendar Event Details

Nanowatt processor and power-management-unit co-design by Prof. Mingoo Seok, Columbia University
Friday, May 24
1 p.m. - 2 p.m. Location: ECSS 3.503

Abstract

In this seminar, we present our recent design of 1) a nanowatt processor for a brain implant and 2) a nanowatt power management unit (PMU) to support such nanowatt processor. Recent advances in neuroscience and integrated circuits enables possibilities for long-term brain-computer-interface (BCI) implants. These long-term BCI implants need on-implant processing since it can reduce wireless data communication and enable a closed-loop operation. Here, we present a Neural Spike Processor (NSP) for motor intention decoding. It performs the novel algorithms for spike sorting and decoding that we optimized for 1-2 order higher computational efficiency. Combined with deeply-scaled supply (0.3V), the NSP consumes only 600 nW while performing always-on end-to-end decoding operation. On the other hand, this nanowatt processor imposes new challenges on designing a PMU. An ideal PMU would support dynamic voltage scaling (DVS) and low-input voltage scalability along with dynamic load regulation and total power minimization. In this work, we introduce hybrid EDAC and TRC based control, which controls the integrated switched-capacitor DCDC converter for powering the NSP. The processor-PMU system is prototyped in a 0.18 µm CMOS, demonstrating the lowest power dissipation by 20X over a prior work yet the highest level of functional integration.

 

Bio

Mingoo Seok is an associate professor of Electrical Engineering at Columbia University. He received the BS from Seoul National University, South Korea, in 2005, and the MS and Ph.D. degree from the University of Michigan in 2007 and 2011, respectively, all in electrical engineering. His research interests are various aspects of VLSI circuits and architecture, including ultra-low-power integrated systems, cognitive and machine-learning computing, adaptive technique for the process, voltage, temperature variations, and transistor wear-out, event-driven controls, and hybrid continuous and discrete computing. He won the 2015 NSF CAREER award and 2019 Qualcomm Faculty Award. He is the technical program committee members for multiple conferences including IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), and International Symposium on Low-Power Electronics and Design (ISLPED). He has been as an associate editor for IEEE Transactions on Circuits and Systems Part I (TCAS-I) (2014-2016), IEEE Transactions on VLSI Systems (TVLSI) (2015-present) and for IEEE Solid-State Circuits Letter (SSCL) (2017-present) and a guest associate editor for IEEE Journal of Solid-State Circuits, the Special Issue for ISSCC 2019.

Contact Info:
Donna, 972-883-5556
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