Comet Calendar, The Official Event Calendar for UT Dallas http://www.utdallas.edu/calendar/rss.php en-us This week's events for Engineering and Computer Science at UT Dallas Notice of Final Oral Examination ~ Guangmo Tong ~ Computer Science http://www.utdallas.edu/calendar/event.php?id=1220440849?WT.mc_id=CalendarRSS http://www.utdallas.edu/calendar/event.php?id=1220440849?WT.mc_id=CalendarRSS Monday, May 21
(10 a.m.)

All Faculty Are Invited to the Final Examination of

 

Guangmo Tong

Graduate Program in Computer Science

May 21, 2018, 10:00 a.m., ECSS 4.910

 

Title of Dissertation:

Optimization Problems in Social Networks

 

Student’s Supervising Committee:

Ding-Zhu Du, Chair

Cong Liu, Co-Chair

András Faragó

Weili Wu

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Notice of Final Oral Examination ~ Aaron Dangerfield ~ Materials Science and Engineering http://www.utdallas.edu/calendar/event.php?id=1220441075?WT.mc_id=CalendarRSS http://www.utdallas.edu/calendar/event.php?id=1220441075?WT.mc_id=CalendarRSS Friday, May 25
(9:30 a.m.)

All Faculty Are Invited to the Final Examination of

 

Aaron Dangerfield

Graduate Program in Materials Science and Engineering

March 28, 2018, 1 p.m., SPN 1.121

 

Title of Dissertation:

Film Formation Mechanisms and Interfacial Interactions Derived From In-Situ Fourier-Transform Infrared Spectroscopy and EX-SITU XPS

 

Student’s Supervising Committee:

Yves J. Chabal, Chair

Amy V. Walker

Jiyoung Kim

Eric Garfunkel

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Sub-baud-rate Clock and Data Recovery Architectures by Professor Pavan Hanumolu, U of Illinois,Urbana-Champaign http://www.utdallas.edu/calendar/event.php?id=1220440825?WT.mc_id=CalendarRSS http://www.utdallas.edu/calendar/event.php?id=1220440825?WT.mc_id=CalendarRSS Friday, May 25
(1 p.m. - 2 p.m.)

Abstract: Clock and data recovery (CDR) is a quintessential function that needs to be performed in all serial communication systems. As data rates increase, the implementation of CDR circuits is becoming very challenging. Classical techniques based on 2x oversampling are becoming inefficient as they require multiple clock phases at very high frequencies. In this e-workshop, I’ll present alternative methods that use baud- and sub-baud-rate architectures. I will begin with a description of baud-rate CDR principles and will extend them to implementing sub-baud-rate CDRs that can recover clock and data using only a quarter-rate clock. I’ll then present circuit implementation details and conclude with the presentation of experimental results obtained from a prototype CDR.


Bio: Pavan Hanumolu is currently a Professor in the Department of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign. He received the Ph.D. degree from the School of Electrical Engineering and Computer Science at Oregon State University, in 2006, where he subsequently served as a faculty member till 2013. Dr. Hanumolu’s research interests are in energy-efficient integrated circuit implementation of analog and digital signal processing, sensor interfaces, wireline communication systems, and power conversion.

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