
"DefectBased Reliability Analysis
for MissionCritical Software" F.Bastani, IL Yen, V.Challagulla,
24th IEEE Computer Society International Computer Software and Applications Conference, Taiwan

Audio Structuring and Personalized Retrieval Using Ontologies,
in Proc. of IEEE Advances in Digital Libraries, Washington, D.C., May 2000
L.Khan, D. McLeod.

Effective Retrieval of Audio Information from Annotated Text Using Ontologies,
to appear in ACM SIGKDD Workshop on Multimedia Data Mining, Boston, MA, August 2000
L.Khan, D. McLeod.
 Disambiguation of Annotated Text of Audio using
Onologies,
to appear in ACM SIGKDD Workshop on Text Mining, Boston, MA, August 2000 L.
Khan, D. McLeod.
 "On Some Reliability Estimation Problems in Random and Partition Testing",
IEEE Transactions on Software Engineering, Vol. 19, No. 7, pp. 687697,
July 1993. S. Ntafos, J. Duran and M. Tsoukalas).
 A ProbeBased Technique to Optimize Join Queries in Distributed Internet
Databases in International Journal of Knowledge and Information Systems
(KAIS) by SpringerVerlag, Volume 2, 2000, Number 3, Pages 373385 (with
C. Shahabi and D. McLeod).
 "The Cost of Software Failures", Proc. of IASTED Software Engineering
Conference, pp. 5357, Nov. 1997. S. Ntafos
 "On Random and Partition Testing", Proc. ISSTA98 in ACM SIGSOFT Software
Engineering Notes, Vol. 23, No. 2, pp. 4248, March 1998. S. Ntafos
 "On Comparisons of Random, Uniform, and Proportional Partition Testing",
manuscript. S. Ntafos
 Jiacun Wang, Yi Deng and Chun Jin, “Compositional modeling and performance
evaluationof traffic control systems via stochastic timed Petri nets”, International
Journal of Software Engineering and Knowledge Engineering, In press
(December 2000).
 J. Wang, Y. Deng and M. Zhou, “Component Time Petri Nets and
Reduction Rules”, IEEE Transactions on
System, Man and Cybernetics, Vol. 30, Part B, No. 4. August 2000.
 J. Wang, G. Xu and Y. Deng. "Reachability Analysis of Real Time
Systems Based on Time Petri Nets", IEEE Transactions on System, Man and
Cybernetics, Vol. 30, Part B,
No.5, Oct. 2000.
 X. He and Y. Deng, "Specifying Software Architecture Connectors in
SAM", International Journal on Software Engineering and Knowledge
Engineering, in press, 2000.
 J. Wang, X. He and Y. Deng, "Introducing Software Architectural
Specification and Analysis in SAM through an Example", Information
and Software Technology  An International Journal, Vol. 41, No. 7,
451567, 1999.
 Y. Deng and J. Wang, "Integrated Architectural Modeling and
Analysis for HighAssurance Command and Control System Design", Annals
of Software Engineering, Vol. 7, 4770, 1999.
 J. Wang, M. Zhou and Y. Deng, "Modeling and Throughput Analysis of
Discrete Event Systems Based on Stochastic Petri Nets", International
Journal of Intelligent Control and Systems, Vol.3, No. 3, 343358, 1999.
 J. Wang and Y. Deng, “Incremental modeling and verification of
flexible manufacturing systems”, International
Journal for Intelligent Manufacturing, Vol. 10, No. 6, 485502, 1999.
 Y. Deng, and C.R. Yang, “Architecturedriven modeling of realtime
concurrent systems with applications in FMS”, Journal of Systems and Software, 45:6178, 1999.
 Y.Deng, S.K. Chang, and X. Lin, “Executable specification and
analysis for the design of concurrent objectoriented systems”, International
Journal of Software Engineering and Knowledge Engineering, Vol. 4, No. 4,
December 1994, 427450.
 T. Znati, Y. Deng, B. Field, and S.K. Chang, “A multilevel
specification and protocol simulation tool for distributed multimedia
communications”, International Journal
in Computer Simulation, Vol. 3, No. 4, 1993, 355382.
 Y. Deng and S.K. Chang, “A framework for specification, modeling and
prototyping of distributed information systems”, International
Journal of Software Engineering and Knowledge Engineering, Vol.1, No.3,
September 1991, 203226.
 Y. Deng and S.K. Chang, “A GNet model for knowledge
representation and reasoning”, IEEE
Transactions on Knowledge and Data Engineering, Vol. 2, No. 3, September
1990, 295310
 K. Beznosov and Y. Deng, “Engineering applicationlevel access
control in distributed systems”, to appear in Handbook of Software Engineering and Knowledge Engineering, World
Scientific Press, 2000.
 K. Beznosov, L. Espinal and Y. Deng, “Performance considerations for
a CORBAbased application
authorization service”, Proceedings of IASTED International Conference
Software Engineering and Applications, Las Vegas, Nevada, November 2000.
 J. Wang, G. Xu and Y. Deng. Reduction rules for components in SAM,
Proceedings of the Fifth International Conference on Integrated Design
and Process Technology, Dallas, Texas, June, 2000
 D. Xu and Yi
Deng, “Modeling Mobile Agent Systems with High Level Petri Nets”,
Proceedings of IEEE International
Conference on Systems, Man and Cybernetics, 2000.
 X. He, F. Zeng and Y. Deng, "Specifying Software Architecture
Connectors in SAM", (best paper) Proceedings of 11^{th} International Conference on Software
Engineering and Knowledge Engineering, Kaiserslautern, Germany, June 1999.
 K. Wreder and Y. Deng, "ArchitectureCentered Enterprise System
Development and Integration Based on Distributed Object Technology
Standard", Proceedings of 23^{rd}
IEEE COMPSAC Conference, Phoenix, USA, October 1999, 250258.
 K. Beznosov, Y. Deng, et al, "A Resource Access Decision Service
for CORBAbased Distributed Systems", Proceedings of IEEE Annual Computer Security Applications Conference,
Phoenix, Arizona, December 1999, 310319.
 K. Beznosov and Y. Deng, "A Framework for Implementing Rolebased
Access Control Using CORBA Security Service", Proceedings
of 4^{th} ACM RoleBased Access Control Workshop, October 1999,
1930.
 J. Wang, C. Jin and Y. Deng, "Performance Evaluation of Traffic
Control Systems via Stochastic Time Petri Nets", Proceedings
of 23^{rd} IEEE COMPSAC Conference, Phoenix, Arizona, October
1999, 436441.
 J. Wang, C. Jin and Y. Deng, "Performance Evaluation of Traffic
Control Networks via Stochastic Time Petri Nets", Proceedings
of IEEE International Conference on Engineering of Complex Computer Systems,
Las Vegas, Nevada, October 1999.
 Y. Deng, J. Wang and R. Sinha, "Incremental Architectural Modeling
and Verification of RealTime Concurrent Systems", Proceedings
of 2^{nd} IEEE International Conference on Formal Engineering Methods,
Brisbane, Australia, December 1998.
 Y. Deng and J. Wang, "Integrated Architectural Modeling of
RealTime Systems with Applications in FMS", Proceedings of 10^{th} International Conference on Software
Engineering and Knowledge Engineering, San Francisco Bay, USA, June 1998,
3443.
 I.L. Yen, F.B. Bastani, and D. Taylor, ``A systematic approach for
developing faulttolerant programs in multiple server systems,'' accepted by
IEEE Trans. Software Engineering.
 ILing Yen, Iftikhar Ahmed, Ramanujam Jagannath, and Sreeparna Kundu,
``The Design and Implementation of a Customizable Fault Tolerance
Framework,'' Journal on Software Engineering and Knowledge Engineering,
Vol. 9, 1999.
 IL. Yen, R. Paul, and K. Mori, ``Guest editors' introduction: Integrated
design, development, and evaluation methods for high assurance systems,'' IEEE
Computer, April 1998.
 IL. Yen and I.R. Chen, ``Reliability assessment of multipleagent
cooperating systems,'' IEEE Trans. Reliability, Sep. 1997.
 IL. Yen, ``A
highly safe selfstabilizing mutual exclusion algorithm,'' Information
Processing Letters, 57, 1996, pp. 301305.
 I.R. Chen and I.L. Yen, ``Analysis of probabilistic error checking
procedures on storage systems,'' Computer Journal, vol. 38, No. 5,
1995, pp. 348354.
 I.L. Yen and F.B. Bastani, ``Parallel hashing: Collision resolution
strategies and performance,'' Journal of Parallel and Distributed
Computing, vol. 31, Dec. 1995, pp. 190198.
 I.L. Yen, E.L. Leiss, and F.B. Bastani, ``Exploiting redundancy for
performance speedup in parallel systems,'' IEEE Parallel and
Distributed Technology, Nov. 1993, pp. 5160.
 F.B. Bastani, I.L. Yen, and I.R. Chen, ``A class of inherently
faulttolerant distributed programs,'' IEEE Trans. Soft. Eng., Oct.
1988, pp. 14321442.
 A. Moitra, S.S. Iyengar, F.B. Bastani, and I.L. Yen, ``Multilevel data
structures: Models and performance,'' IEEE Trans. Softw. Eng. June
1988, pp. 858867.
 F.B. Bastani, I.L. Yen, and S.S. Iyengar, ``Concurrent maintenance of
data structures in a distributed environment,'' The Comp. Journal,
Vol. 31, No. 2, 1988, pp. 165174.
 ILing Yen, IngRay Chen, and Biao Chen, ``Realtime atomic transaction
processing using multiinvariant data structure,'' IEEE High Assurance
Systems Engineering Symposium, Washington D.C., Nov. 1999.
 F.B. Bastani, V.L. Winter, and I.L. Yen, ``Dependability of relational
safetycritical programs,'' IEEE Intl. Symp. on Software Reliability
Engineering, Boca Raton, Florida, Nov. 1999.
 Biao Chen, Jiang Zhang, ILing Yen, Bing Liu, ``Study of traffic
interactions in queue sharing to support differentiated services,'' Intl.
Conf. on Parallel and Distributed Computing and Systems, Cambridge,
Massachusetts, Nov. 1999.
 Farokh Bastani, Vikram Reddy, Punarvasu Srigiriraju, ILing Yen, ``A
relational program architecture for the Bay Area Rapid Transit (BART)
system,'' IEEE Conf. on HighIntegrity Systems, Albuquerquq, New
Mexico, Nov. 1999.
 ILing Yen and Hitesh Kapoor, ``A 2Phase NModular Redundancy
Algorithm,'' Workshop on ObjectOriented Reliable and Dependable Systems
(WORDS'99), Newport Beach, California, Jan. 1999.
 ILing Yen, Iftikhar Ahmed, Ramanujam Jagannath, and Sreeparna Kundu, ``Implementation
of a Customizable Fault Tolerance Framework,'' IEEE International
Symposium on ObjectOriented RealTime Distributed Computing, Kyoto,
Japan, April, 1998.
 IL. Yen and K. Karun, ``Implementation
and performance assessment of multilevel data structures,'' 21st
International Computer Software and Applications Conference (COMPSAC'97),
Bethesda, Maryland, August, 1997
 ILing Yen, ``An ObjectOriented SNMR Framework for Dependable Systems,'' Workshop
on ObjectOriented Reliable and Dependable Systems (WORDS'97), Newport
Beach, California, Feb. 1997.
 I.L. Yen, ``Fault Tolerance via Specialization: An Efficient Approach for
Tolerating General Failures,'' Intl. Design and Technology Processing
Conference, Austin, Texas, Dec. 1996.
 I.L. Yen, ``Specialized
NModular Redundant Processors in LargeScale Distributed Systems,'' 15th
Symposium on Reliable Distributed Systems, Niagaraonthelake,
Ontario, Canada, Oct. 1996.
 I.L. Yen, ``Multiple invariant system design for faulttolerant realtime
applications,'' Workshop on ObjectOriented RealTime Dependable Systems,
Laguna Beach, California, Feb. 1996.
 I.L. Yen and I.R. Chen, ``Quality assessment for multiple server
cooperating systems,'' Proceedings COMPSAC, Dallas, TX, Aug. 1995,
pp. 218223.
 I.L. Yen and F.B. Bastani, ``A highly safe selfstabilizing mutual
exclusion algorithm,'' 2nd Workshop on SelfStabilizing Systems,
Las Vegas, NV, May 2829, 1995.
 I.L. Yen and F.B. Bastani, ``Robust parallel resource management in
shared memory multiprocessor systems,'' International Parallel
Processing Symposium, Santa Barbara, CA, April 1995, pp. 458465.
 I.L. Yen and F.B. Bastani, ``On efficiently tolerating general failures
in autonomous decentralized multiserver systems,'' International
Symposium on Autonomous Decentralized Systems, Phoenix, AZ, April 1995,
pp. 288296.
 I.L. Yen and I.R. Chen, ``A systematic approach for integration of
multimedia capabilities in consulting systems,'' Pacific Workshop on
Distributed Multimedia Systems, Hawaii, March 1995.
 Y.K. Chu, I.L. Yen, and D. Rover, ``Guiding processor allocation with
estimated execution time for mesh connected multiple processor systems,'' Hawaii
International Conference on System Sciences, Hawaii, Jan. 1995.
 I.L. Yen, I.R. Chen, and F.B. Bastani, ``Reliability assessment for the
design of dependable soft realtime cooperating systems,'' Workshop on
ObjectOriented RealTime Dependable Systems, Oct. 1994, Dana Point,
CA, pp. 134139.
 Y.Y. Fang, I.L. Yen, R.M. Dubash, ``Improving the performance of Lee's
maze routing algorithm on parallel computers,'' Symposium on Parallel
and Distributed Processing, Las Vegas, NV, Oct. 1994.
 Y.K. Chu, I.L. Yen, and D. Rover, ``Incorporating job scheduling for
processor allocation on twodimensional meshconnected systems,'' Symposium
on Parallel and Distributed Processing, Las Vegas, NV, Oct. 1994.
 I.L. Yen and F.B. Bastani, ``Systematic incorporation of efficient fault
tolerance in systems of cooperating parallel programs,'' 24th Intl. Symp.
FaultTolerant Computing, Austin, TX, June 1994, pp. 154163.
 I.L. Yen, M.K. Jeng, I.R. Chen, ``Processor allocation for parallel
objectoriented programs,'' 1993 Intl. Conf. Parallel and Distributed
Systems, Taipei, Taiwan, Dec. 1993, pp. 212216.
 I.L. Yen and F.B. Bastani, ``Robust coordination in distributed
multiserver systems,'' Workshop on Advances in Parallel and Distributed
Systems, Princeton, NJ, Oct. 1993, pp. 133138.
 I.L. Yen, R.M. Dubash, and F.B. Bastani, ``Strategies for mapping Lee's
maze routing algorithms onto parallel architectures,'' Proceedings IPPS,
Los Angeles, CA, April 1993, pp. 672679.
 I.L. Yen and F.B. Bastani, ``Inherent fault tolerance in decentralized
processcontrol systems,'' Intl. Symp. on Autonomous Decentralized
Systems, Kawasaki, Japan, Mar. 1993, pp. 267274.
 I.L. Yen, E.L. Leiss, and F.B. Bastani, ``A repetitive fault tolerance
model for parallel programs,'' Hawaii Conf. on System Sciences,
Hawaii, Jan. 1993, pp. 447455.
 I.L. Yen, T. AlMarzooq, F.B. Bastani, and E.L. Leiss, ``Information
hiding in parallel programs: Model and experimental evaluation on the
Connection Machine,'' Symp. Frontiers of Massively Parallel Computations,
McLeans, VA, October 1992, pp. 326333.
 R.M. Dubash, F.B. Bastani, and I.L. Yen, ``Fault tolerant process
planning and control,'' Proceedings COMPSAC, Chicago, IL, Sep.
1992, pp. 188193.
 I.L. Yen and F.B. Bastani, ``Hash table in massively parallel systems,'' Proceedings
IPPS, Los Angeles, CA, March 1992, pp. 660664.
 I.L. Yen, E.L. Leiss, and F.B. Bastani, ``An inherently faulttolerant
sorting algorithm,'' Proceedings IPPS, Los Angeles, CA, April 1991.
 I.L. Yen, ``Massively parallel hash algorithms and performance,'' Proceedings
CSC, San Antonio, TX, March 1991.
 I.L. Yen, F.B. Bastani, and E.L. Leiss, ``High performance massively
parallel abstract data type components,'' Proceedings COMPSAC,
Chicago, IL, Oct. 1990, pp. 196201.
 I.L. Yen, D.R. Leu, and F.B. Bastani, ``Hash table and sorted array: A
case study of multientry data structures in massively parallel systems,'' Symp.
Frontiers of Massively Parallel Computations, McLeans, VA, March 1990,
pp. 5154.
 I.L. Yen, F.B. Bastani, and Y. Zhao, ``On selfstabilization,
nondeterminism, and inherent fault tolerance,'' MCC Workshop on
SelfStabilization, Austin, TX, August 1989.
 F.B. Bastani and I.L. Yen, ``A faulttolerant replicated storage
system,'' Proceedings Data Eng., Los Angeles, CA, Feb. 1987.
 F.B. Bastani and I.L. Yen, ``Impact of parallel processing on software
quality,'' Proceedings SuperComputing Systems, Florida, Dec. 1985.
 F.B. Bastani and I.L. Yen, ``Analysis of an inherently faulttolerant
program,'' Proceedings COMPSAC, Chicago, IL, Oct. 1985.
 "On Deciding Readiness and Failure Equivalences for Processes",
(with Lu Tian), Information and Computation 117, pp. 193205, 1995.
 "Deciding Branching Bisimilarity of Normed ContextFree Processes
Is in Sigma(2)", (with D. Caucal and L. Tian), Information and
Computation 118, pp. 306315, 1995.
 "A note on the Complexity of Deciding Bisimilarity of Normed Unary
Processes", (with Lu Tian), Theoretical Computer Science 131,
pp. 441448, 1994.
 "On Deciding Some Equivalences for Concurrent Processes",
(with Lu Tian), RAIRO Theoretical Informatics and Applications 27,
pp. 5171, 1994.
 "Deciding Bisimilarity of Normed ContextFree Processes is in
Sigma(2)", (with Lu Tian), Theoretical Computer Science 123,
pp. 183197, 1994.
 "On Deciding Readiness and Failure Equivalences for Processes",
(with Lu Tian), to appear in Information and Computation.
 "On the Rearrangeability of Switching Networks Composed of Digital
Symmetrical Matrices", (with Hai Nguyen), Proc. 5th Intern. Conf.
on Computing and Information, pp. 155159, Sudbury, Canada, 1993.
 "On the Complexity of Bisimilarity of Normed Probabilistic ContextFree
Processes", (with Lu Tian), Proc. 5th Intern. Conf. on Computing
and Information, pp. 37, Sudbury, Canada, 1993.
 "On Deciding Trace Equivalence for Processes", (with Lu Tian),
Information Sciences 72, pp. 105121, 1993.
 "The Complexity of Deciding Code and Monoid Properties for Regular
Sets", International Journal of Algebra and Computation, Vol.
2, pp. 3955, 1992.
 "On Some Equivalence Relations for Probabilistic Processes",
(with Lu Tian), Fundamenta Informaticae 17, pp. 211234, 1992.
 "NonUniform Complexity and the Randomness of Certain Complete
Languages", Theoretical Computer Science, Vol. 96, pp. 305324,
1992.
 "The Parallel Complexity of Coarsest Set Partition Problems",
(with Sang Cho), Information Processing Letters, Vol. 42, pp. 8994,
1992.
 "Efficient Detectors and Constructors for Simple Languages",
International Journal of Foundations of Computer Sciences, Vol.
2, pp. 183205, 1992.
 "The Parallel Complexity of Finite State Automata Problems",
(with Sang Cho), Information and Computation, Vol. 97, pp. 122,
1992.
 "The Effective Entropies of Some Extensions of ContextFree Languages",
Information Processing Letters, Vol. 37, pp. 165169, 1991.
 "A Note on Separating DeterministicTimeComplexity Classes, and
on AlmostEverywhere Complex Sets", (with J. Geske and J. Seifera),
Information and Computation, Vol. 92, pp. 97104, 1991.
 "Finite Automaton Aperiodicity is PSPACEComplete",
(with Sang Cho), Theoretical Computer Science, Vol. 88, pp. 99116,
1991.
 "Effective Entropies and Data Compression", Information
and Computation, Vol. 90, pp. 6785, 1991.

``Communication Reduction in Multiple Multicasts based on
Hybrid StaticDynamic Scheduling,"
(with D. R. Surma and P. M. Kogge)
Accepted for publication in IEEE Transactions on Parallel and Distributed
Systems.

``Optimizing Overall Loop Schedules using Prefetching and Partitioning,''
(with F. Chen, and T. W. O'Neil)
Accepted for publication in
IEEE Transactions on Parallel and Distributed Systems.

``Efficient Acceptable Design Exploration Based on Module Utility
Selection,"
(with C. Chantrapornchai, and X. Sharon Hu)
in IEEE Transactions on Computer Aided Design of
Integrated Circuits and Systems, Vol. 19, No. 1, Jan. 2000, pp. 1929
.

``Probabilistic Loop Scheduling for Applications with Uncertain
Execution Time,"
(with S. Tongsima, C. Chantrapornchai, D. Surma and N. Passos)
in
IEEE Transactions on Computers, Vol. 49, No. 1,
Jan. 2000, pp. 6580.

``Properties and Algorithms for Unfolding of Probabilistic
Dataflow Graphs,"
(with S. Tongsima, T. W. O'Neil, and C. Chantrapornchai)
Accepted for publication in
Journal of VLSI Signal Processing.

``Efficient Module Selections for
Finding Highly Acceptable Designs based on Inclusion Scheduling,''
(with C. Chantrapornchai, and X. S. Hu)
Accepted for publication in
Journal of Systems Architecture.

``Optimizing Page Replacement for MultipleLevel Memory Hierarchy,"
(with C. Chantrapornchai) in
International Journal of Computers and Their Applications
Vol. 6, No. 4, Dec. 1999, pp. 212222.

``Scheduling of Uniform MultiDimensional Systems
under Resource Constraints,"
(with N. Passos) in
IEEE Transactions on VLSI Systems,
Vol. 6, No. 4, December 1998, pp. 719730.

``Collision Graph based Communication Scheduling for
Parallel Systems,"
(with D. R. Surma)
in International Journal of Computers and Their Applications. Vol. 5, No. 1, March 1998.

``Rotation Scheduling: A Loop Pipelining Algorithm,"
(with L.F. Chao and A. LaPaugh)
in IEEE Transactions on Computer Aided Design ,
Vol. 16, No. 3, March 1997, pp. 229239.

``Efficient Loop Scheduling and Pipelining for Applications with
Nonuniform Loops,"
(with S. Tongsima, C. Chantrapornchai, and N. Passos)
in
IASTED International Journal of Parallel and Distributed Systems and
Networks,
Vol. 1, No 4, 1998, pp. 204211.

``Reducing Data Hazards on Multipipelined DSP
Architecture with Loop Scheduling,"
(with S. Tongsima, C. Chantrapornchai and N. Passos)
in
Journal of VLSI Signal Processing,
Vol. 18, 1998, pp. 111123.

``Communication Sensitive Loop Scheduling for DSP Applications,"
(with S. Tongsima and N. Passos),
(regular paper),
IEEE Transactions on Signal Processing
Vol. 45, No. 5, May 1997, pp. 13091322.

``MultiDimensional Interleaving for Synchronous Circuit Design
Optimization,"
(with N. Passos and L.F. Chao),
(regular paper), IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems,
Vol. 16, No. 2, February 1997, pp. 146159.

``Minimization of Memory Access Overhead for Multidimensional
DSP Applications via Multilevel Partitioning and Scheduling,"
(with Q. Wang and N. Passos),
Accepted for publication (regular paper),
IEEE Transactions on Circuits and Systems II.
Vol. 44, No. 9, September 1997,
pp. 741753.

``Hardware/Software Codesign With the HMS Framework,"
(with M. Sheliga)
(regular paper), in
Journal of VLSI Signal Processing Systems,
Vol. 13, No. 1, August 1996, pp. 3756.

``Achieving Full Parallelism using MultiDimensional Retiming,"
(with N. Passos) (regular paper),
IEEE Transactions on Parallel and Distributed Systems,
Vol. 7, No. 11, November 1996, pp. 11501163.

``Synchronous Circuit Optimization via MultiDimensional Retiming,"
(Part 1)
(Part 2)
(with N. Passos), (regular paper),
in
IEEE Transactions on Circuits and Systems, vol II 
Analog and Signal Processing,
Vol. 43, No. 7, July 1996,
pp. 507519.

``Optimizing DSP Flow Graphs via ScheduleBased MultiDimensional Retiming,"
(with N. Passos and S. C. Bass),
IEEE Transactions on Signal Processing, Vol. 44, No. 1,
January, 1996, pp. 150156.

``Optimal Data Scheduling for Uniform Multidimensional
Applications,"
(with Q. Wang, and N. Passos)
IEEE Transactions on Computers, Vol. 45, No. 12,
December 1996, pp. 14391444.

``Static Scheduling for Synthesis of DSP Algorithms on Various Models,"
<
br>
(with L.F. Chao), (regular paper)
Journal of VLSI Signal Processing, Vol 10, pp 207223, 1995.

``Scheduling DataFlow Graphs via Retiming and Unfolding,"
(with L.F. Chao)
in (regular paper)
IEEE Transactions on Parallel and Distributed
Systems Vol. 8, No. 12, December 1997, pp. 12591267.

``Maintaining Bipartite Matchings in the Presence of Failures,''
(with K. Steiglitz), (regular paper)
Networks Journal, Vol. 23, no. 5, Aug. 1993, pp. 459471.

``Reconfigurability and Reliability of
Systolic/Wavefront Arrays,''
(with K. Steiglitz), (regular paper)
IEEE Transactions on Computers, vol. 42, no. 7, July, 1993,
pp. 854862.

``Error Detection in Arrays via Dependency Graphs,''
(with K. Steiglitz), (regular paper)
Journal of VLSI Signal Processing, vol. 4, no. 4,
October 1992, pp 331342.

Z. Yu, E. H.M. Sha, N. Passos and R. Ju,
``Algorithms and Architecture Support for Pipelining and Scheduling
Nested Loopw with Conditions,"
submitted to
IEEE Transactions on Computers.

T. W. O'Neil, S. Tongsima, and E. H.M. Sha,
``Extended Retiming: A Graph Transformation Technique
for Optimal Scheduling of DataFlow Graphs,"
submitted to IEEE Transactions on Parallel and
Distributed Systems.

F. Chen, T. W. O'Neil, and E. H.M. Sha,
``Optimizing
Overall Loop Schedules using Prefetching and Partitioning,''
submitted to IEEE Transactions on Parallel and
Distributed Systems.

``A Fully Parallel Design Methodology for
MultiDimensional DSP Applications,"
(with M. Sheliga and N. Passos)
submitted to
Journal of VLSI Signal Processing.

``Efficient PolynomialTime Nested Loop Fusion with Full Parallelism,"
(with N. Passos and T. O'Neil)
submitted to
IEEE Transactions on Parallel and Distributed
Systems .

"Rapid Prototyping Implementation and Optimization based on
Conceptual Specification for Fuzzy Applications,"
(with C. Chantrapornchai, M. Sheliga and S. Tongsima)
submitted to to Journal of Fuzzy Sets
and Systems.

D. Surma, E. H.M. Sha and N. Passos,
``Communication Scheduling with Rerouting based on
Static and Hybrid Techniques,"
submitted to Journal of Circuits, Systems and Computers.
Referred Conference Papers

Z. Wang, M. Kirkpatrick, and E. H.M. Sha,
``Optimal Two Level Partitioning and Loop Scheduling for Hiding Memory
Latency for DSP Applications,"
in Proc. ACM
37th Design Automation Conference , Los Angeles, California, June, 2000

J. Ding, J. C. Furgeson and Edwin H..M. Sha,
``Application Specific Image Compression for Virtual Conferencing,"
in Proc. IEEE International Conference on Information
Technology: Coding and Computing,
Las Vegas, Nevada, March 2000.

J. Ding, M. Kirkpatrick, and E. H.M. Sha,
``QoS Measures and Implementations Based on Various Models for
Realtime Communications,"
in Proc. 3rd IEEE Symposium on ApplicationSpecific Systems
and Software Engineering Technology,
Richardson, Texas, March, 2000.

C. Chantrapornchai, E. H.M. Sha and S. X. Hu,
``Efficient Algorithms for Acceptable Design Exploration,"
in Proc. IEEE Tenth Great Lakes Symposium on VLSI,
Evanston, Illinois, March, 2000.

V. Andronache, E. H.M. Sha and N. Passos,
``Design and Analysis of Efficient ApplicationSpecific
Online Page Replacement Techniques,"
in Proc. IEEE Tenth Great Lakes Symposium on VLSI,
Evanston, Illinois, March, 2000.

T. W. O'Neil, and Edwin H.M. Sha,
``RateOptimal Graph
Transformation Based on Extended Retiming and Unfolding,"
in Proc. 11th IASTED International Conference
on Parallel and Distributed Computing and Systems,
Cambridge, MA, November 1999.

Z. Wang, V. Andronache, and Edwin H.M. Sha ,
``Optimal Partitioning under Memory Constraints for Minimizing Average Schedule
Length,"
in Proc. 11th IASTED International Conference
on Parallel and Distributed Computing and Systems,
Cambridge, MA, November 1999.

F. Chen, and E. H.M. Sha,
``Loop Scheduling and Partitions for Hiding Memory Latencies,"
in Proc. IEEE 12th International Symposium on System
Synthesis}, San Jose, CA, November 1999.

T. O'Neil, S. Tongsima, and E. H.M. Sha,
``Optimal Scheduling of DataFlow Graphs Using Extended Retiming,"
in Proc. ISCA 12th International Conference on Parallel
and Distributed Computing Systems,
Fort Lauderdale, Florida, August, 1999.

N. L. Passos, R. Light, V. Andronache, E. H.M. Sha,
``Design of 2D Filters using a Parallel Processor Architecture,"
in Proc. ISCA 12th International Conference on Parallel
and Distributed Computing Systems,
Fort Lauderdale, Florida, August, 1999.

T. O'Neil, S. Tongsima, and and E. H.M. Sha,
``Extended Retiming: Optimal Scheduling via a GraphTheoretical Approach,"
in Proc. 1999 IEEE International Conference On
Acoustics, Speech, and Signal Processing,
Phoenix, Arizona, March 1999, Vol. 4, pp. 20012004.

S. Tongsima, T. O'Neil, and E. H.M. Sha,
``Unfolding Probabilistic Dataflow Graphs Under Different Timing Models,"
in Proc. 1999 IEEE International Conference On
Acoustics, Speech, and Signal Processing,
Phoenix, Arizona, March 1999, Vol 4, pp. 18891892.

T. Zhou, X. S. Hu and Edwin H.M. Sha,
``A Probabilistic Performance Metric for RealTime System Design ,"
in Proc. 1999 7th International Workshop on Hardware Software CoDesign, Rome, Italy, May 1999, pp. 9094.

T. Zhou, X. S. Hu and Edwin H.M. Sha,
``Probabilistic Performance Estimation for Realtime Embedded Systems,"
in Proc. 1999 ACM/IEEE International Workshop on Timing Issues
in the Specification and Synthesis of Digital Systems,
Monterey, California, March, 1999, pp. 8388.

C. Chantrapornchai, E. H.M. Sha, and X. S. Hu,
``Efficient Algorithms for Finding Highly Acceptable
Designs Based on ModuleUtility Selections,"
in Proc. IEEE 9th Great Lakes Symposium on VLSI, Ann
Arbor, Michigan, March, 1999, pp. 128131.

Y. Tian, E. H.M. Sha, C. Chantrapornchai, and P. M. Kogge,
``Efficient Data Placement and Replacement Algorithms
for MultipleLevel Memory Hierarchy,"
in Proc.
10th International Conference on Parallel and Distributed Computing
and Systems, Las Vegas, Nevada, October, 1998, pp. 196201.

F. Chen, S. Tongsima, and E. H.M. Sha,
``Loop Scheduling Optimization with Data Prefetching based on
Multidimensional Retiming,"
in Porc. ISCA 11th International Conference on Parallel
and Distributed Computing Systems,
Chicago, Illinois, pp. 129134.

F. Chen, S. Tongsima, and E. H.M. Sha,
``Loop Scheduling Algorithm for Timing and Memory Operation Minimization
with Register Constraint,''
in Proc. 1998 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS),
Boston, Massachusetts, October, 1998.

C. Chantrapornchai, E. H.M. Sha and S. X. Hu,
``Efficient Scheduling for Imprecise Timing Based on Fuzzy Theory,"
in Proc. 1998 Midwest Symposium on Circuit and Systems,
Notre Dame, Indiana, August, 1998.

Andrea Leonardi, Nelson L. Passos, and Edwin H.M. Sha,
``Nested Loops Optimization for Multiprocessor Architecture Design",
in Proc. 1998 Midwest Symposium on Circuit and Systems,i
Notre Dame, Indiana, August, 1998.

S. Tongsima, C. Chantrapornchai, E. H.M. Sha and N. Passos
`` Optimizing Circuits with Confidence Probability using
Probabilistic Retiming,"
in Proc. IEEE International Conference on Circuits
and Systems, Monterey, California, June, 1998

D. R. Surma, E. H.M. Sha and P. M. Kogge,
``Compiletime Priority Assignment and Rerouting for Communication
Minimization in Parallel Systems,"
in Proc. IEEE International Conference on Circuits
and Systems, Monterey, California, June, 1998

M. Sheliga, T. Yu, F. Chen, and E. H.M. Sha,
``Graph Transformation for Communicaton Minimization Using
Retiming,"
in Proc. IEEE International Conference on Circuits
and Systems, Monterey, California, June, 1998

T. Z. Yu, F. Chen and E. H.M. Sha,
``Loop Scheduling Algorithms for Power Reduction,"
in Proc. IEEE
International Conference on Acoustics, Speech, and Signal Processing,
Seattle, Washington, May 1998.

C. Chantrapornchai, S. Tongsima, E. H.M. Sha and
S. X. Hu,
``Dealing with Impreciseness in Architectural Synthesis,"
in Proc. IASTED International Conference on
Artificial Intelligence and Soft Computing, Cancun, Mexico, May, 1998.

Y. Tian, E. H.M. Sha, C. Chantrapornchai and P. M. Kogge,
``Optimizing Data Scheduling on ProcessorInMemory Arrays,"
in Proc. IEEE 12th International Parallel Processing
Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.

S. Tongsima, C. Chantrapornchai, and E. H.M. Sha,
``Probabilistic Loop Scheduling Considering Communication
Overhead,"
in Proc. 4th Workshop on Job Scheduling Strategies
for Parallel Processing,
with IEEE 12th International Parallel Processing
Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.

D. Surma and E. H.M. Sha,
``ProjectBased approach to teaching Microprocessors
and their Applications,"
in American Society for Engineering Education
1998 Spring Conference,
Detroit, Michigan, April, 1998.

K. Wang, T. Yu and E. H.M. Sha,
``RCRS: A Framework for Loop Scheduling with Limited Number of Registers,"
in Proc. IEEE 8th Great Lakes Symposium on VLSI,
Lafayette, Louisiana, February, 1998.

``SCORE: An efficient technique to reduce
congestion in Parallel Systems,"
(with D. Surma and P. M. Kogge)
in 10th International Conference on Parallel and Distributed
Computing Systems, New Orleans, LA, October, 1997.

``Efficitent Data Placement for ProcessorInMemory Array Processors,"
(with Y. Tian, C. Chantrapornchai, and P. M. Kogge)
in Proc. 9th International Conference on Parallel
and Distributed Computing
and Systems, Washington, D.C., October, 1997.

``Efficitent Loop Scheduling and Pipelining for Applications with
Nonuniform Loops,"
(with S. Tongsima, C. Chantrapornchai, and N. Passos)
in Proc. 9th International Conference on Parallel
and Distributed Computing
and Systems, Washington, D.C., October, 1997.

``Probabilistic Rotation: Scheduling Graphs with
Uncertain Execution Time,"
(with S. Tongsima, C. Chantrapornchai and N. Passos)
in Proc. 1997 International Conference on
Parallel Processing, Bloomingdale, Illinois, Aug., 1997.

``Rapid System Design Framework for Fuzzy Applications''
(with C. Chantrapornchai, M. Sheliga and S. Tongsima)
in Proc. IEEE
40th Midwest Symposium on Circuits and Systems,
Sacramento, California, August, 1997.

``Efficient Communication Scheduling with Rerouting based
on Collision Graphs,"
(with D. Surma)
in Proc. 1997 Annual International
Symposium on High Performance Computing Systems, Winnipeg,
Manitoba, Canada, July 1012, 1997, pp. 483492.

``Hardware/Software Codesign for Video
Compression Using the EXECUBE Processor Array,"
(with M. Sheliga and P. Kogge)
in Proc. 1997 IEEE National Aerospace and
Electronics Conference,
Dayton, Ohio, July, 1997.

``Imprecise Task Schedule Optimization,"
(with C. Chantrapornchai, and S. Tongsima)
in Proc. the Sixth IEEE International
Conference on Fuzzy Systems, Barcelona, Spain,
July, 1997.

``Hybrid StaticDynamic Communication Scheduling for Parallel
Systems"
(with D. Surma)
in Proc. 1997 ACM Symposium on Applied Computing, San Jose,
California, Feb. 1997, pp. 374379..

"Algorithms and Hardware Support for Branch Anticipation,"
(with T. Yu, N. Passos and R. D.C. Ju)
in Proc. IEEE Great Lakes Symposium on VLSI,
Urbana, Illinois, March 1997, pp. 163168.

"Scheduling with Confidence for Probabilistic Data Flow
Graphs,"
(with S. Tongsima, C. Chantrapornchai, and N. Passos)
in Proc. IEEE Great Lakes Symposium on VLSI,
Urbana, Illinois, March 1997, pp. 150155.

``SHARP: Efficient Loop Scheduling with Data Hazard
Reduction on Multiple Pipeline DSP Systems,"
(with S. Tongsima, C, Chantrapornchai and N. Passos)
in Proc. 1996 IEEE Workshop on VLSI Signal Processing,
San Fransisco, California, November, 1996, pp. 253262.

``VHDL Synthesis of MultiDimensional Applications: a New Approach,"
(with N. Passos) in
Proc. 1996 IEEE International Conference on Computer Designs,
Austin, Texas, October, 1996, pp. 530535.

``Polynomialtime Nested Loop Fusion with Full Parallelism,"
(with C. Lang and N. Passos) (regular paper) in
Proc. 1996 International
Conference on Parallel Processing, August 1996, Vol 3, pp. 916.

``Static Communication Scheduling for Minimizing Collisions
in Application Specific Parallel Systems,"
(with D. Surma) (regular paper) in
Proc.
1996 International Conference on Applicationspecific Systems,
Architectures and Processors, Chicago, Illinois, August 1996, pp. 240249.

``Hardware/Software Codesign for DSP Applications
via the HMS Framework."
(with Mike Sheliga)
in Proc. IEEE
International Conference on Acoustics, Speech, and Signal Processing,
Atlanta, Georgia, May, 1996, Vol. 2, pp. 12481251.

``Optimal Communication Scheduling Based on Collision Graph Model,"
(with D. Surma and S. Tongsima)
in Proc. IEEE
International Conference on Acoustics, Speech, and Signal Processing,
Atlanta, Georgia, May, 1996, Vol. 6, pp. 33193322.

``Rapid Prototyping for Fuzzy Systems,"
(with C. Chantrapornchai and S. Tongsima),
in Proc. IEEE Great Lakes Symposium on VLSI,
Ames, Iowa, March 1996
pp. 234239.

``A Parameterized IndexGenerator for the MultiDimensional Interleaving
Optimization,"
(with N. Passos), in
Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996,
pp. 6671.

``Minimization of Fuzzy Systems based on Fuzzy Inference Graph,"
(with C. Chantrapornchai and S. Tongsima)
in
Proc. IEEE International Symposium on Circuits and Systems,
Atlanta, Georgia, 1996, Vol. 4, pp. 651654.

``Fully Parallel Hardware/Software Codesign for MultiDimensional DSP
Applications,"
(with M. Sheliga and N. Passos)
in Proc. 4th IEEE International Workshop on
Hardware/Software Codesign, Pittsburgh, Pennsylvania,
March, 1996, pp. 1825.

``PushUp Scheduling: Optimal PolynomialTime Resource Constrained
Scheduling for MultiDimensional Applications,"
(with N. Passos)
in Proc. IEEE/ACM International Conference on ComputerAided Design,
San Jose, California, November, 1995, pp. 588591.

``Multilevel Partitioning and Scheduling under Local Memory Constraint," <
br>
(with Q. Wang and N. Passos)
in
Proc. IEEE Symposium on Parallel
and Distributed Processing, (long paper),
San Antonio, Texas, Dec, 1995, pp. 612619.

``Fully Parallel Synchronous Circuit Design using MultiDimensional
Interleaving,"
(with N. Passos and L.F. Chao)
in Proc. IEEE Iinternational Conference on Computer
Design, Austin, Texas, October, 1995, pp 440445.

``Integrating Selective FaultTolerance into Hard RealTime
Multiprocessor Schedules,"
(with N. M. Sabine)
in
Proc. IEEE International Conference on Parallel and
Distributed Computing Systems,
Orlando, Florida, September, 1995, pp. 8994.

``ApplicationSpecific Communication Scheduling on Parallel Systems,"
(with D. R. Surma)
in
Proc. IEEE International Conference on
Parallel and Distributed Computing Systems,
Orlando, Florida, September, 1995, pp. 137139.

``ArchitectureDependent Loop Scheduling via CommunicationSensitive
Remapping,"
(with S. Tongsima and N. Passos),
in Proc. International Conference on Parallel Processing,
Wisconsin, August, 1995, pp. 97104.

``MemoryEfficient Fully Parallel Loop Transformation,"
(with N. Passos and L.F. Chao),
in Proc. International Conference on Parallel Processing,
Wisconsin, August, 1995, pp. 182185.

``Optimizing Synchronous Systems for Multidimensional Applications,"
(with N. Passos and L.F. Chao),
in Proc. IEEE European Design and Test Conference, Paris, France,
March, 1995, pp 5458.

``Improving SelfTimed Pipeling Ring Performance Through The
Addition of Buffer Loops,"
(with Hai Zhao and N. M. Sabine),
in Proc. IEEE Great Lakes Symposium on VLSI,
March, 1995, pp 218223
(regular paper).

``Bus Minimization and Scheduling of MultiChip Modules,"
(with M. Sheliga),
in
Proc. IEEE Great Lakes Symposium on VLSI, Buffalo, New York,
March, 1995, pp 4045 (regular paper).

``Memory/Time Optimization of 2D Filters,"
(with N. Passos),
in Proc.
IEEE International Conference on Acoustics, Speech and Signal
Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 32233226.

``RateOptimal Scheduling for CycloStatic and Periodic Schedules,"
(with L.F. Chao),
in Proc.
IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 32313234.

``Communication Sensitive Rotation Scheduling,"
(with S. Tongsima and N. Passos)
in Proc. 1994 IEEE International Conference on Computer
Design, Cambridge, Massachusetts, October, 1994, pp 150153.

``Full Parallelism of Uniform Nested Loops by MultiDimensional Retiming,"
(with N. Passos)
in Proc.
1994 International Conference on Parallel Processing, vol. 2, St. Charles,
Illinois, August, 1994, pp. 130133.

``Loop Pipelining for Scheduling Multidimensional Systems via Rotation,"
(with N. Passos and S. C. Bass)
in Proc. IEEE/ACM 1994 Design Automation Conference
(nominated for the Best Paper Award, 13 nominated out of 439 papers),
San Diego, California, June, 1994, pp. 485490.

`` Retiming and Clock Skew for Synchronous Systems,"
(with L.F. Chao)
in
Proc. IEEE 1994 Interenational Symposium on
Circuits and Systems, London, England, May, 1994, vol. 1, pp. 283286.

`` Partitioning and Retiming of Multidimensional Systems,"
(with N. Passos and S. C. Bass)
in Proc. IEEE 1994 Interenational Symposium on
Circuits and Systems, London, England, May, 1994, vol. 4, pp. 227230.

``Global Node Reduction of Linear Systems Using Ratio Analysis,"
(with M. Sheliga)
in Proc. IEEE Seventh International Symposium on
HighLevel Synthesis,
NiagaraontheLake, Canada, May, 1994, pp. 140145.

``ScheduleBased MultiDimensional Retiming on DataFlow Graphs,"
(with N. Passos and S. C. Bass)
in Proc. 1994 International Parallel Processing Symposium,
Cancun, Mexico, April, 1994, pp. 195199.

`` Rotation Scheduling: A Loop Pipelining Algorithm,''
(with L.F. Chao and A. LaPaugh)
in
Proc. 30th ACM/IEEE Design Automation Conference,
(nominated for the Best Paper Award), Dallas, Texas, June 1993,
pp. 566572.

``RateOptimal Static Scheduling for DSP DataFlow Programs",
(with L.F. Chao),
in
Proc. IEEE Third Great Lakes Symposium on VLSI,
March 1993, pp 8084.

``Efficient Retiming and Unfolding,"
(with L.F. Chao)
in
Proc. 1993 IEEE Int'l Conf. on Acoustic, Speech, and
Signal Processing, Minneapolis, Minnesota, April, 1993, pp. I421I424.

``Static Scheduling of Uniform Nested Loops,"
(with L.F. Chao),
in
Proc. 7th International Parallel Processing Symposium, Newport Beach, California, April, 1993, pp.254258.

``Maintaining Bipartite Matchings in the Presence of Failures,''
(with K. Steiglitz),
in
Proc. of 7th International Parallel
Processing Symposium, (Long Paper), Newport Beach,
California, April, 1993, pp. 5764.

``Unified Static Scheduling on Various Models,"
(with L.F. Chao),
in
Proc. 1993 International Conference on Parallel Processing,
St. Charles, Illinois, August 1993, pp. II 231235.

``Retiming and Unfolding DataFlow Graphs,"
(with L.F. Chao),
Proc. 1992 International Conference on Parallel Processing,
St. Charles, Illinois, August 1992, pp. II 3340.

``Scheduling Cyclic DataFlow Graphs by Retiming with Resource Constraints,"
(with L.F. Chao and A. LaPaugh),
ACM/IEEE Sixth International Workshop on HighLevel Synthesis,
Dana Point, California, November 1992, pp. 111134.

``Algorithms for MinCut Linear Arrangements of Outerplanar graphs"
(with L.F. Chao),
Proc. 1992 IEEE Int'l Symposium on Circuits and Systems,
San Diego, California, May 1992, pp. 18511854.

``An ErrorDetectable Array for AllSubstring Comparison,"
Proc. 1992 IEEE Int'l Symposium on Circuits and Systems,
San Diego, California, May 1992, pp 29412944.

``RunTime Error Detection in Arrays Based on the DataDependency Graph,"
(with K. Steiglitz),
Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and
Signal Processing,
San. Francisco, March 1992, Vol. 5, pp. 625628.

``Unfolding and Retiming DataFlow DSP Programs for RISC Multiprocessor
Scheduling"
(with L.F. Chao),
Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and
Signal Processing,
San Francisco, California, March 1992, Vol. 5, pp. 565568.

``Efficient Distributed Reconfiguration for Binary Trees on Diogenes Model,"
(with L.F. Chao),
Proc. 1992 Int'l Phoenix Conf. on Computers
and Communications,
Scottsdale, Arizona, April 1992, pp. 464471.

``Optimizing Synchronous Systems via Retiming and Unfolding,"
(with L.F. Chao),
Tau 1992: 1992 Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems, March 1992.

``Explicit Constructions for Reliable Reconfigurable Array Architectures,''
(with K. Steiglitz),
Proc. Third IEEE Symposium on Parallel and Distributed Processing,
Dallas, Texas, Dec. 1991, pp. 640647

``Planar Linear Arrangements for Outerplanar graphs,"
(with L.F. Chao),
Proc. 1991 Second Great Lakes Computer Science Conference,
Kalamazoo, Michigan, Oct. 1991.

``Design for Easily Applying Test
Vectors to Improve Delay Fault Coverage,''
(with L.F. Chao),
Proc. 1991 IEEE Int'l Conf. on ComputerAided Design,
Santa Clara, California, Nov. 1991, pp. 500503.

``Reconfigurability and Reliability of Systolic/Wavefront Arrays,''
(with K. Steiglitz),
Proc. 1991 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing,
Toronto, Canada, May 1991, Vol. 2, pp. 10011004.
