Publications

 
 

Books & Book Chapters

 
  1. Y. Chiu, Analysis and Design of CMOS Pipelined Analog-to-Digital Converter, Springer-Verlag (TBP, ISBN: 0387270396)
  2. Y. Chiu, Analysis and Design of Successive-Approximation Analog-to-Digital Converter, Springer-Verlag (TBP)
  3. Y. Chiu, "Adaptive Signal Processing Techniques for Analog-to-Digital Converters," in Sampling Theory, A Renaissance, edited by Götz Pfander, Springer-Verlag, (TBP, 2014)
  4. Y. Chiu, "Digitally Assisted Analog Techniques for Data Converters," in Design of Mixed-Signal Integrated Circuits in Scaled CMOS Process: Digitally Assisted Analog and Analog Assisted Digital Techniques, edited by X. Jiang, (TBP, 2014)
 

Journal & Magazine Articles (refereed)

 
  1. S.-C. Lee and Y. Chiu, “A 15-MHz bandwidth 1-0 MASH SD ADC with nonlinear memory error calibration achieving 85-dBc SFDR,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 695-707, Mar. 2014.
  2. G. Wang, F. Kacani, and Y. Chiu, “IRD digital background calibration of SAR ADC with coarse reference ADC acceleration,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, pp. 11-15, Jan. 2014.
  3. Y. Chiu, “On the operation of CMOS active-cascode gain stage,” Journal of Computer and Communications, vol. 1, no. 6, pp. 18-24, Nov. 2013.
  4. H. Xu, D. Gong, and Y. Chiu, “A comparative study of amplitude and timing estimation in experimental particle physics using Monte Carlo simulation,” Journal of Modern Physics, vol. 4, no. 5B, pp. 42-47, May 2013.
  5. Y. Chiu, “A digital stochastic gradient-ascent maximum power-point tracking technique for photovoltaic applications,” i-manager's Journal on Digital Signal Processing, vol. 2, no. 1, pp. 30-34, Apr.-Jun. 2013.
  6. Y. Chiu, S.-C. Lee, and W. Liu, “An ICA framework for digital background calibration of analog-to-digital converters,” Sampling Theory in Signal and Image Processing (STSIP), SampTA 2011 special issue, vol. 11, no. 2-3, pp. 253-270, 2012.
  7. W. Liu and Y. Chiu, “Time-interleaved analog-to-digital conversion with online adaptive equalization,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, pp. 1384-1395, Jul. 2012.
  8. S. Hoyos, B. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, and B. Nikolic, “A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 split-control, fast coarse locking digital DLL in 0.13μm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, pp. 564-568, Mar. 2012.
  9. W. Liu, P. Huang, and Y. Chiu, “A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 2661-2672, Nov. 2011. (Most read/downloaded JSSC article of November 2011)
  10. P. Huang, S.-K. Hsien, V. Lu, P. Wan, S.-C. Lee, W. Liu, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, “SHA-less pipelined ADC with in-situ background clock-skew calibration,” IEEE Journal of Solid-State Circuits, special issue of CICC 2010, vol. 46, pp. 1893-1903, Aug. 2011.
  11. Y. Chiu, “Equalization techniques for nonlinear analog circuits,” IEEE Communications Magazine, vol. 49, pp. 132-139, Apr. 2011.
  12. S.-C. Lee and Y. Chiu, “Digital calibration of capacitor mismatch errors in sigma-delta modulators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, pp. 690-698, Apr. 2011.
  13. B. Peng, H. Li, P. Lin, and Y. Chiu, “An offset double conversion technique for digital calibration of pipelined ADCs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, pp. 961-965, Dec. 2010.
  14. B. Peng, H. Li, S.-C. Lee, P. Lin, and Y. Chiu, “A virtual-ADC digital background calibration technique for multistage A/D conversion,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, pp. 853-857, Nov. 2010.
  15. R. Tseng, H. Li, D.-H. Kwon, Y. Chiu, and A. S. Y. Poon, “A four-channel beamforming down-converter in 90-nm CMOS utilizing phase-oversampling,” IEEE Journal of Solid-State Circuits, special issue of ASSCC 2009, vol. 45, pp. 2262-2272, Nov. 2010.
  16. S.-C. Lee and Y. Chiu, “Digital calibration of nonlinear memory errors in sigma–delta modulators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, pp. 2462-2475, Sep. 2010.
  17. D.-H. Kwon, H. Li, Y. Chang, R. Tseng, and Y. Chiu, “Digitally equalized CMOS transmitter front-end with integrated power amplifier,” IEEE Journal of Solid-State Circuits, special issue of CICC 2009, vol. 45, pp. 1602-1614, Aug. 2010.
  18. H. Li, D.-H. Kwon, D. Chen, and Y. Chiu, “A fast digital predistortion algorithm for radio-frequency power amplifier linearization with loop delay compensation,” IEEE Journal of Selected Topics in Signal Processing, vol. 3, issue 3, pp. 374-383, Jun. 2009.
  19. W. Liu and Y. Chiu, “Background digital calibration of successive approximation ADC with adaptive equalisation,” Electronics Letters, vol. 45, issue 9, pp. 456-458, Apr. 2009.
  20. P. Huang and Y. Chiu, “Calibration of sampling clock skew in SHA-less pipeline ADCs,” Electronics Letters, vol. 44, issue 18, pp. 1061-1062, Aug. 2008.
  21. R. Tseng, A. S. Poon, and Y. Chiu, “A mixed-signal vector modulator for eigen-beamforming receivers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, pp. 479-483, May 2008.
  22. Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE Journal of Solid-State Circuits, special issue of ISSCC 2004, vol. 39, pp. 2139-2151, Dec. 2004.
  23. Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, “Least-mean-square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE Transactions on Circuits and Systems I, special issue of advances on analog-to-digital and digital-to-analog converters, vol. 51, pp. 38-46, Jan. 2004.
  24. Y. Chiu, “Inherently linear capacitor error-averaging techniques for pipelined A/D conversion,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 229-232, Mar. 2000.
  25. Y. Chiu, B. Jalali, S. Garner, and W. Steier, “Broadband electronic linearizer for externally modulated analog fiber-optic links,” IEEE Journal of Photonics Technology Letters, vol. 11, pp. 48-50, Jan. 1999.
 

Conference Papers (refereed)

 
  1. H. Xu, D. Gong, and Y. Chiu, “On the performance of linear optimal filter and Wiener filter for signal detection in liquid ionization calorimeters,” to appear in IEEE Nuclear Science Symposium (NSS’14), Seattle, WA, 2014.
  2. Y. Zhou, H. Xu, Y. Chiu, D. Gong, T. Liu, and J. Ye, “High-speed, high-resolution, radiation-tolerant SAR ADC for particle physics experiments,” in Topical Workshop on Electronics for Particle Physics (TWEPP’14), Aix-en-Provence, France, 2014.
  3. B. Wu and Y. Chiu, “An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS,” in IEEE Custom Integrated Circuits Conference, CICC’14, San Jose, CA, 2014.
  4. B. Wu, S. Zhu, Y. Zhou, and Y. Chiu, “A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system,” in IEEE Custom Integrated Circuits Conference, CICC’14, San Jose, CA, 2014.
  5. J. Song, M. He, A. Enteshari, and Y. Chiu, “A motion-artifact rejection and stabilization (MARS) technique for bioelectronic interface circuits and systems,” in SRC TECHCON 2014, Austin, TX, 2014.
  6. (Invited) S. Sarkar, Y. Zhou and Y. Chiu, “PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy,” in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’14), College Station, TX, 2014.
  7. Y. Zhou, B. Xu, and Y. Chiu, “A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration,” in IEEE Symposium on VLSI Circuits, VLSI’14, Honolulu, Hawaii, 2014.
  8. (Invited) Y. Chiu, “On the operation of CMOS active-cascode gain stage,” in 2013 Electronics and Circuits Conference (ECC'13), Sanya, China, 2013.
  9. (Invited) B. Elies, F. Kacani, S.-C. Lee, and Y. Chiu, “Modeling and digital correction of summing-node leakage in SAR ADCs,” in International Workshop on Design Automation for Analog and Mixed-Signal Circuits, co-located with IEEE International Conference on Computer-Aided Design, ICCAD’13, San Jose, CA, 2013.
  10. H. Xu, Y. Chiu, and D. Gong, “A linear optimal filtering approach for pileup noise removal in high-rate liquid ionization calorimeters,” in 2013 IEEE Nuclear Science Symposium (NSS’13), Seoul, S. Korea, 2013.
  11. G. Wang and Y. Chiu, “Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering,” in IEEE Custom Integrated Circuits Conference, CICC’13, San Jose, CA, 2013.
  12. (Invited) Y. Zhou and Y. Chiu, “Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC,” in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’13), Columbus, OH, 2013.
  13. (Invited) Y. Chiu, W. Liu, P. Huang, F. Kacani, G. Wang, B. Elies, and Y. Zhou, “Digital calibration of SAR ADC,” in 10th International Conference on Sampling Theory and Applications, SampTA’13, Bremen, Germany, 2013.
  14. H. Xu, D. Gong, and Y. Chiu, “A comparative study of amplitude and timing estimation in experimental particle physics using Monte Carlo simulation,” in 2013 Spring International Conference on Advances in Physics (CAP-S), Wuhan, China, 2013.
  15. B. Xu and Y. Chiu, “Background calibration of time-interleaved ADC using direct derivative information,” in IEEE International Symposium on Circuits and Systems, ISCAS’13, Beijing, China, 2013.
  16. (Invited) Y. Chiu, “Demystifying bilateral feedback analysis,” in IEEE International Conference on Solid-State and Integrated-Circuit Technology, ICSICT’12, Xi'an, China, 2012.
  17. H. Li, G. Wang, and Y. Chiu, “Real-time FPGA emulation for fast verification of adaptive AMS circuits,” in International Workshop on Design Automation for Analog and Mixed-Signal Circuits, co-located with IEEE International Conference on Computer-Aided Design, ICCAD’12, San Jose, CA, 2012.
  18. J. Song, B. Zhu, and Y. Chiu, “Online calibration of interface characteristic variation in capacitively coupled non-contact EEG acquisition system,” in IEEE EMBS Dallas First Annual Texas Medical Device Symposium, Dallas, TX, 2012.
  19. W. Liu, P. Huang, and Y. Chiu, “A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration,” in IEEE Custom Integrated Circuits Conference, CICC’12, San Jose, CA, 2012. (Recipient of the CICC Best Regular Paper Award)
  20. S.-C. Lee, B. Elies, and Y. Chiu, “An 85dB SFDR 67dB SNDR 8OSR 240MS/s SD ADC with nonlinear memory error calibration,” in IEEE Symposium on VLSI Circuits, VLSI’12, Honolulu, Hawaii, 2012.
  21. (Invited) Y. Chiu, “A framework of digital-domain background calibration of multi-step ADC using pseudorandom test signal injection,” in 9th International Conference on Sampling Theory and Applications, SampTA'11, Singapore, 2011.
  22. P. Huang, S.-K. Hsien, V. Lu, P. Wan, S.-C. Lee, W. Liu, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, “SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration,” in IEEE Custom Integrated Circuits Conference, CICC’10, San Jose, CA, 2010. (Intel/CICC Student Scholarship Award for being one of the highest rated student papers)
  23. P. Wan, Y. Chiu, and P. Lin, “A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3,” in IEEE Custom Integrated Circuits Conference, CICC’10, San Jose, CA, 2010.
  24. W. Liu, P. Huang, and Y. Chiu, “A 12bit 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR,” in IEEE International Solid-State Circuits Conference, ISSCC’10, San Francisco, CA, 2010.
  25. Y. Chiu and X. Luo, “Direct-sequence maximum power-point tracker for photovoltaic sources,” in IEEE Power and Energy Conference, PECI’10, Urbana, IL, 2010.
  26. G. D. Nguyen, Y. Chiu, and M. Feng, “24-GHz low noise amplifier using coplanar waveguide series feedback in 130-nm CMOS,” in IEEE Asia-Pacific Microwave Conference, APMC’09, Singapore, 2009.
  27. R. Tseng, H. Li, D.-H. Kwon, A. S. Y. Poon, and Y. Chiu, “An inherently linear phase-oversampling vector modulator in 90-nm CMOS,” in IEEE Asian Solid-State Circuits Conference, ASSCC’09, Taipei, Taiwan, 2009.
  28. (Invited) Y. Chiu, D.-H. Kwon, and H. Li, “Design trade-offs for digitally equalized CMOS RF transmitter,” in IEEE International Conference on ASIC, ASICON’09, Changsha, China, 2009.
  29. D.-H. Kwon, H. Li, Y. Chang, R. Tseng, and Y. Chiu, “CMOS RF transmitter with integrated power amplifier utilizing digital equalization,” in IEEE Custom Integrated Circuits Conference, CICC’09, San Jose, CA, 2009.
  30. W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, “A 600MS/s 30mW 0.13μm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization,” in IEEE International Solid-State Circuits Conference, ISSCC’09, San Francisco, CA, 2009. (Winner of the 46th DAC/ISSCC Student Design Contest)
  31. H. Li, D.-H. Kwon, and Y. Chiu, “A fast digital adaptive predistortion and loop-delay compensation algorithm for RF power amplifier linearization,” in IEEE Power Amplifier Symposium, PAS’09, San Diego, CA, 2009.
  32. (Invited) Y. Chiu, “Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters,” in IEEE International Conference on Solid-State and Integrated-Circuit Technology, ICSICT’08, Beijing, China, 2008.
  33. S. Hoyos, B. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, and B. Nikolic, “A 15 MHz-600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS,” in IEEE European Solid-State Circuits Conference, ESSCIRC’08, Edinburgh, UK, 2008.
  34. B. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, and B. Nikolic, “Background ADC calibration in digital domain,” in IEEE Custom Integrated Circuits Conference, CICC’08, San Jose, CA, 2008.
  35. D.-H. Kwon, H. Li, and Y. Chiu, “Efficiency and linearity enhancement of CMOS RF power amplifiers using adaptive baseband digital predistortion,” in IEEE International Symposium on VLSI Design, Automation & Test, VLSI-DAT’08, Hsinchu, Taiwan, 2008.
  36. R. Tseng, A. S. Y. Poon, and Y. Chiu, “A mixed-signal MIMO beamforming receiver”, in IEEE Radio and Wireless Symposium, RWS’08, Orlando, FL, 2008.
  37. P. Bhoraskar and Y. Chiu, “A 6.1-mW dual-loop digital DLL with 4.6-ps rms jitter using window-based phase detector,” in IEEE Asian Solid-State Circuits Conference, ASSCC’07, Jeju, Korea, 2007.
  38. W. Liu and Y. Chiu, “An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters,” in IEEE International Conference on ASIC, ASICON’07, Guilin, China, 2007.
  39. P. Huang and Y. Chiu, “A gradient-based digital algorithm for sampling clock skew calibration of SHA-less pipeline ADCs,” in IEEE International Symposium on Circuits and Systems, ISCAS’07, New Orleans, LA, 2007.
  40. B. Tsang, Y. Chiu, and B. Nikolic, “A 1.2V, 10.8mW, 500kHz sigma-delta modulator with 84dB SNDR and 96dB SFDR,” in IEEE Symposium on VLSI Circuits, VLSI’06, Honolulu, Hawaii, 2006.
  41. (Invited) Y. Chiu, B. Nikolic, and P. R. Gray, “Scaling of analog-to-digital converters into ultra-deep-submicron CMOS,” in IEEE Custom Integrated Circuits Conference, CICC’05, San Jose, CA, 2005.
  42. Y. Chiu, P. R. Gray, and B. Nikolic, “A 1.8V 14b 10MS/s pipelined ADC in 0.18μm CMOS with 99dB SFDR,” in IEEE International Solid-State Circuits Conference, ISSCC’04, San Francisco, CA, 2004. (Recipient of the ISSCC Jack Kilby Outstanding Student Paper Award)
  43. Y. Chiu, B. Jalali, S. Garner, and W. Steier, “Broadband linearization of externally modulated fiber-optic links,” in IEEE International Topical Meeting on Microwave Photonics, MWP’98, Princeton, NJ, 1998.
  44. Y. Chiu and B. Jalali, “Improving dynamic range of AM optical modulator by 1-GHz CMOS predistortion circuit,” in IEEE OptoElectronics and Communications Conference, OECC’98, Chiba, Japan, 1998.